2013/5/15 jean-philippe francois <jp.francois@xxxxxxxxxx>:
> Hi,
>
> I am working on a dm3730 based camera.
> The sensor input clock is provided by the cpu via the CAM_XCLK pin.
> Here is the corresponding log :
>
> [ 9.115966] Entering cam_set_xclk
> [ 9.119781] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to 24685714 Hz
> [ 9.121337] ov10x33 1-0010: sensor id : 0xa630
> [ 10.293640] Entering cam_set_xclk
> [ 10.297149] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to 0 Hz
> [ 10.393920] Entering cam_set_xclk
> [ 10.397979] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to 24685714 Hz
>
> However, when mesured on the actual pin, the frequency is around 30 MHz
>
> The crystal clock is 19.2 MHz
> All this was correct with 3.6.11.
>
Sorry for the resend, wrong tab and enter key sequence in gmail ...
It seems the dpll4_m5_ck is not correctly set,
3.6.11 code in isp.c (without error handling)
r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
CM_CAM_MCLK_HZ/divisor);
...
r = clk_enable(isp->clock[ISP_CLK_CAM_MCLK]);
3.9 code in isp.c (without error handling)
r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK],
CM_CAM_MCLK_HZ/divisor);
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
The PLL settings ie multiplier and divisor are the same in each case,
but the dmesg output differ :
Here is what happens when isp_enable_clock is called on 3.6
3.6
[ 10.133697] Entering cam_set_xclk
[ 10.137573] clock: clksel_round_rate_div: dpll4_m5_ck
target_rate 172800000
[ 10.137573] clock: new_div = 5, new_rate = 172800000
[ 10.137603] clock: dpll4_m5_ck: set rate to 172800000
[ 10.138061] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to
24685714 Hz
3.9
[ 9.095581] Entering cam_set_xclk
[ 9.102661] omap3isp omap3isp: isp_set_xclk(): cam_xclka set to
24685714 Hz
So the frequency setting register are correctly set, but the actual
output frequency is not.
maybe dpll4 is not correctly locked ? I will also check
isp_enable_clock is really called.
But I suppose it is, because except for the frequency, everything is
working correctly.
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