From: Rajendra Nayak <rnayak@xxxxxx>
Add the clock tree related data for OMAP54xx platforms.
Cc: Paul Walmsley <paul@xxxxxxxxx>
Signed-off-by: Rajendra Nayak <rnayak@xxxxxx>
Signed-off-by: Benoit Cousson <b-cousson@xxxxxx>
[santosh.shilimkar@xxxxxx: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
---
As mentioned in the summary, this patch will be updated once the
movement of clock data to drivers/clock is clear.
arch/arm/mach-omap2/cclock54xx_data.c | 1794 +++++++++++++++++++++++++++++++
arch/arm/mach-omap2/clock.h | 23 +-
arch/arm/mach-omap2/clock54xx.h | 12 +
arch/arm/mach-omap2/clock_common_data.c | 139 ++-
4 files changed, 1931 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/mach-omap2/cclock54xx_data.c
create mode 100644 arch/arm/mach-omap2/clock54xx.h
diff --git a/arch/arm/mach-omap2/cclock54xx_data.c b/arch/arm/mach-omap2/cclock54xx_data.c
new file mode 100644
index 0000000..a1e2800
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock54xx_data.c
@@ -0,0 +1,1794 @@
+/*
+ * OMAP54xx Clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul@xxxxxxxxx)
+ * Rajendra Nayak (rnayak@xxxxxx)
+ * Benoit Cousson (b-cousson@xxxxxx)
+ * Mike Turquette (mturquette@xxxxxx)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@xxxxxxxxxxxxxxx mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock54xx.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "cm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prm-regbits-54xx.h"
+#include "control.h"
+#include "scrm54xx.h"
+
+/* OMAP4 modulemode control */
+#define OMAP54XX_MODULEMODE_HWCTRL 0
+#define OMAP54XX_MODULEMODE_SWCTRL 1
+
+/* Root clocks */
+
+DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
+
+DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
+ OMAP54XX_CM_CLKSEL_ABE, OMAP54XX_PAD_CLKS_GATE_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
+
+DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
+ OMAP54XX_CM_CLKSEL_ABE, OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
+
+static const struct clksel_rate div_1_5_rates[] = {
+ { .div = 1, .val = 5, .flags = RATE_IN_54XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div_1_6_rates[] = {
+ { .div = 1, .val = 6, .flags = RATE_IN_54XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div_1_7_rates[] = {
+ { .div = 1, .val = 7, .flags = RATE_IN_54XX },
+ { .div = 0 },
+};
+
+static const struct clksel sys_clkin_sel[] = {
+ { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
+ { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
+ { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
+ { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
+ { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
+ { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
+ { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
+ { .parent = NULL },
+};
+
+static const char *sys_clkin_parents[] = {
+ "virt_12000000_ck",
+ "virt_13000000_ck",
+ "virt_16800000_ck",
+ "virt_19200000_ck",
+ "virt_26000000_ck",
+ "virt_27000000_ck",
+ "virt_38400000_ck",
+
+};
+
+DEFINE_CLK_MUX(sys_clkin, sys_clkin_parents, NULL, 0x0, OMAP54XX_CM_CLKSEL_SYS,
+ OMAP54XX_SYS_CLKSEL_SHIFT, OMAP54XX_SYS_CLKSEL_WIDTH,
+ CLK_MUX_INDEX_ONE, NULL);
+
+DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
+
+/* Module clocks and DPLL outputs */
+
+static const char *abe_dpll_bypass_clk_mux_parents[] = {
+ "sys_clkin", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL,
+ 0x0, OMAP54XX_CM_CLKSEL_WKUPAON, OMAP54XX_CLKSEL_0_0_SHIFT,
+ OMAP54XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_CLKSEL_ABE_PLL_REF, OMAP54XX_CLKSEL_0_0_SHIFT,
+ OMAP54XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_ABE,
+ .clk_bypass = &abe_dpll_bypass_clk_mux,
+ .clk_ref = &abe_dpll_clk_mux,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_ABE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_ABE,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_ABE,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+
+static const char *dpll_abe_ck_parents[] = {
+ "abe_dpll_clk_mux",
+};
+
+static struct clk dpll_abe_ck;
+
+static const struct clk_ops dpll_abe_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_abe_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_ck,
+ },
+ .dpll_data = &dpll_abe_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
+
+static const char *dpll_abe_x2_ck_parents[] = {
+ "dpll_abe_ck",
+};
+
+static struct clk dpll_abe_x2_ck;
+
+static const struct clk_ops dpll_abe_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+static struct clk_hw_omap dpll_abe_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+static const struct clk_ops omap_hsdivider_ops = {
+ .set_rate = &omap2_clksel_set_rate,
+ .recalc_rate = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, OMAP54XX_CM_DIV_M2_DPLL_ABE,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, 1, 8);
+
+DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
+ OMAP54XX_CM_CLKSEL_ABE, OMAP54XX_CLKSEL_OPP_SHIFT,
+ OMAP54XX_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+ NULL);
+
+DEFINE_CLK_FIXED_FACTOR(abe_iclk, "abe_clk", &abe_clk, 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(abe_lp_clk_div, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, 1, 16);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, OMAP54XX_CM_DIV_M3_DPLL_ABE,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_CORE,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_CORE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_CORE,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_CORE,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+
+static const char *dpll_core_ck_parents[] = {
+ "sys_clkin",
+};
+
+static struct clk dpll_core_ck;
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_core_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_ck,
+ },
+ .dpll_data = &dpll_core_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
+
+static const char *dpll_core_x2_ck_parents[] = {
+ "dpll_core_ck",
+};
+
+static struct clk dpll_core_x2_ck;
+
+static struct clk_hw_omap dpll_core_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h21x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H21_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+static const char *c2c_fclk_parents[] = {
+ "dpll_core_h21x2_ck",
+};
+
+static struct clk c2c_fclk;
+
+static const struct clk_ops c2c_fclk_ops = {
+};
+
+static struct clk_hw_omap c2c_fclk_hw = {
+ .hw = {
+ .clk = &c2c_fclk,
+ },
+};
+
+DEFINE_STRUCT_CLK(c2c_fclk, c2c_fclk_parents, c2c_fclk_ops);
+
+DEFINE_CLK_FIXED_FACTOR(c2c_iclk, "c2c_fclk", &c2c_fclk, 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(custefuse_sys_gfclk_div, "sys_clkin", &sys_clkin, 0x0,
+ 1, 2);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h11x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H11_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h12x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H12_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h13x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H13_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h14x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H14_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h22x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H22_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h23x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H23_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h24x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0,
+ OMAP54XX_CM_DIV_H24_DPLL_CORE, OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
+ OMAP54XX_CM_DIV_M2_DPLL_CORE,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m3x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, OMAP54XX_CM_DIV_M3_DPLL_CORE,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+static const char *iva_dpll_hs_clk_div_parents[] = {
+ "dpll_core_h12x2_ck",
+};
+
+static struct clk iva_dpll_hs_clk_div;
+
+static struct clk_hw_omap iva_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &iva_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents,
+ c2c_fclk_ops);
+
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_IVA,
+ .clk_bypass = &iva_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_IVA,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_IVA,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_IVA,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+
+static struct clk dpll_iva_ck;
+
+static const struct clk_ops dpll_iva_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_iva_ck_hw = {
+ .hw = {
+ .clk = &dpll_iva_ck,
+ },
+ .dpll_data = &dpll_iva_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_iva_ck_ops);
+
+static const char *dpll_iva_x2_ck_parents[] = {
+ "dpll_iva_ck",
+};
+
+static struct clk dpll_iva_x2_ck;
+
+static struct clk_hw_omap dpll_iva_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_iva_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_h11x2_ck, "dpll_iva_x2_ck",
+ &dpll_iva_x2_ck, 0x0, OMAP54XX_CM_DIV_H11_DPLL_IVA,
+ OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_h12x2_ck, "dpll_iva_x2_ck",
+ &dpll_iva_x2_ck, 0x0, OMAP54XX_CM_DIV_H12_DPLL_IVA,
+ OMAP54XX_DIVHS_MASK);
+
+static struct clk mpu_dpll_hs_clk_div;
+
+static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &mpu_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents,
+ c2c_fclk_ops);
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_MPU,
+ .clk_bypass = &mpu_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_MPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_MPU,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_MPU,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+
+static struct clk dpll_mpu_ck;
+
+static struct clk_hw_omap dpll_mpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_mpu_ck,
+ },
+ .dpll_data = &dpll_mpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_iva_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
+ OMAP54XX_CM_DIV_M2_DPLL_MPU,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+DEFINE_CLK_FIXED_FACTOR(per_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 2);
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_PER,
+ .clk_bypass = &per_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_PER,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_PER,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_PER,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+
+static struct clk dpll_per_ck;
+
+static struct clk_hw_omap dpll_per_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_ck,
+ },
+ .dpll_data = &dpll_per_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_iva_ck_ops);
+
+static const char *dpll_per_x2_ck_parents[] = {
+ "dpll_per_ck",
+};
+
+static struct clk dpll_per_x2_ck;
+
+static struct clk_hw_omap dpll_per_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h11x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, OMAP54XX_CM_DIV_H11_DPLL_PER,
+ OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h12x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, OMAP54XX_CM_DIV_H12_DPLL_PER,
+ OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h14x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, OMAP54XX_CM_DIV_H14_DPLL_PER,
+ OMAP54XX_DIVHS_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
+ OMAP54XX_CM_DIV_M2_DPLL_PER,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+ 0x0, OMAP54XX_CM_DIV_M2_DPLL_PER,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m3x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+ 0x0, OMAP54XX_CM_DIV_M3_DPLL_PER,
+ OMAP54XX_DIVHS_0_4_MASK);
+
+/* DPLL_UNIPRO1 */
+static struct dpll_data dpll_unipro1_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1,
+ .clk_bypass = &sys_clkin,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_UNIPRO1,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+
+static struct clk dpll_unipro1_ck;
+
+static struct clk_hw_omap dpll_unipro1_ck_hw = {
+ .hw = {
+ .clk = &dpll_unipro1_ck,
+ },
+ .dpll_data = &dpll_unipro1_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_unipro1_ck, dpll_core_ck_parents, dpll_iva_ck_ops);
+
+static const char *dpll_unipro1_clkdcoldo_parents[] = {
+ "dpll_unipro1_ck",
+};
+
+static struct clk dpll_unipro1_clkdcoldo;
+
+static struct clk_hw_omap dpll_unipro1_clkdcoldo_hw = {
+ .hw = {
+ .clk = &dpll_unipro1_clkdcoldo,
+ },
+ .clksel_reg = OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1,
+};
+
+DEFINE_STRUCT_CLK(dpll_unipro1_clkdcoldo, dpll_unipro1_clkdcoldo_parents,
+ c2c_fclk_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_unipro1_m2_ck, "dpll_unipro1_ck",
+ &dpll_unipro1_ck, 0x0,
+ OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1,
+ OMAP54XX_DIVHS_0_6_MASK);
+
+/* DPLL_UNIPRO2 */
+static struct dpll_data dpll_unipro2_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2,
+ .clk_bypass = &sys_clkin,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_UNIPRO2,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+
+static struct clk dpll_unipro2_ck;
+
+static struct clk_hw_omap dpll_unipro2_ck_hw = {
+ .hw = {
+ .clk = &dpll_unipro2_ck,
+ },
+ .dpll_data = &dpll_unipro2_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_unipro2_ck, dpll_core_ck_parents, dpll_iva_ck_ops);
+
+static const char *dpll_unipro2_clkdcoldo_parents[] = {
+ "dpll_unipro2_ck",
+};
+
+static struct clk dpll_unipro2_clkdcoldo;
+
+static struct clk_hw_omap dpll_unipro2_clkdcoldo_hw = {
+ .hw = {
+ .clk = &dpll_unipro2_clkdcoldo,
+ },
+ .clksel_reg = OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2,
+};
+
+DEFINE_STRUCT_CLK(dpll_unipro2_clkdcoldo, dpll_unipro2_clkdcoldo_parents,
+ c2c_fclk_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_unipro2_m2_ck, "dpll_unipro2_ck",
+ &dpll_unipro2_ck, 0x0,
+ OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2,
+ OMAP54XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_FIXED_FACTOR(usb_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 3);
+
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+ .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_USB,
+ .clk_bypass = &usb_dpll_hs_clk_div,
+ .flags = DPLL_J_TYPE,
+ .clk_ref = &sys_clkin,
+ .control_reg = OMAP54XX_CM_CLKMODE_DPLL_USB,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_USB,
+ .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_USB,
+ .mult_mask = OMAP54XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP54XX_DPLL_DIV_MASK,
+ .enable_mask = OMAP54XX_DPLL_EN_MASK,
+ .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
+ .sddiv_mask = OMAP54XX_DPLL_SD_DIV_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+
+static struct clk dpll_usb_ck;
+
+static const struct clk_ops dpll_usb_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+ .init = &omap2_init_clk_clkdm,
+};
+
+static struct clk_hw_omap dpll_usb_ck_hw = {
+ .hw = {
+ .clk = &dpll_usb_ck,
+ },
+ .dpll_data = &dpll_usb_dd,
+ .clkdm_name = "l3init_clkdm",
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_usb_ck_ops);
+
+static const char *dpll_usb_clkdcoldo_parents[] = {
+ "dpll_usb_ck",
+};
+
+static struct clk dpll_usb_clkdcoldo;
+
+static struct clk_hw_omap dpll_usb_clkdcoldo_hw = {
+ .hw = {
+ .clk = &dpll_usb_clkdcoldo,
+ },
+ .clksel_reg = OMAP54XX_CM_CLKDCOLDO_DPLL_USB,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents, c2c_fclk_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
+ OMAP54XX_CM_DIV_M2_DPLL_USB,
+ OMAP54XX_DIVHS_0_6_MASK);
+
+static const char *dss_syc_gfclk_div_parents[] = {
+ "sys_clkin",
+};
+
+static struct clk dss_syc_gfclk_div;
+
+static struct clk_hw_omap dss_syc_gfclk_div_hw = {
+ .hw = {
+ .clk = &dss_syc_gfclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(dss_syc_gfclk_div, dss_syc_gfclk_div_parents, c2c_fclk_ops);
+
+static struct clk l3_iclk_div;
+
+static struct clk_hw_omap l3_iclk_div_hw = {
+ .hw = {
+ .clk = &l3_iclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l3_iclk_div, iva_dpll_hs_clk_div_parents, c2c_fclk_ops);
+
+DEFINE_CLK_FIXED_FACTOR(func_128m_clk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 16);
+
+DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
+ 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 2);
+
+static const char *gpu_core_gclk_mux_parents[] = {
+ "dpll_core_h14x2_ck", "dpll_per_h14x2_ck",
+};
+
+DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_GPU_GPU_CLKCTRL, OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT,
+ OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_GPU_GPU_CLKCTRL, OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT,
+ OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH, 0x0, NULL);
+
+static const char *gpu_l3_iclk_parents[] = {
+ "l3_iclk_div",
+};
+
+static struct clk gpu_l3_iclk;
+
+static struct clk_hw_omap gpu_l3_iclk_hw = {
+ .hw = {
+ .clk = &gpu_l3_iclk,
+ },
+};
+
+DEFINE_STRUCT_CLK(gpu_l3_iclk, gpu_l3_iclk_parents, c2c_fclk_ops);
+
+static const struct clk_div_table l3init_60m_fclk_rates[] = {
+ { .div = 1, .val = 0 },
+ { .div = 8, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
+ 0x0, OMAP54XX_CM_CLKSEL_USB_60MHZ,
+ OMAP54XX_CLKSEL_0_0_SHIFT, OMAP54XX_CLKSEL_0_0_WIDTH,
+ 0x0, l3init_60m_fclk_rates, NULL);
+
+static const char *wkupaon_iclk_mux_parents[] = {
+ "sys_clkin", "abe_lp_clk_div",
+};
+
+DEFINE_CLK_MUX(wkupaon_iclk_mux, wkupaon_iclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_CLKSEL_WKUPAON, OMAP54XX_CLKSEL_0_0_SHIFT,
+ OMAP54XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *l3instr_ts_gclk_div_parents[] = {
+ "wkupaon_iclk_mux",
+};
+
+static struct clk l3instr_ts_gclk_div;
+
+static struct clk_hw_omap l3instr_ts_gclk_div_hw = {
+ .hw = {
+ .clk = &l3instr_ts_gclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l3instr_ts_gclk_div, l3instr_ts_gclk_div_parents,
+ c2c_fclk_ops);
+
+static struct clk l4_root_clk_div;
+
+static struct clk_hw_omap l4_root_clk_div_hw = {
+ .hw = {
+ .clk = &l4_root_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l4_root_clk_div, gpu_l3_iclk_parents, c2c_fclk_ops);
+
+DEFINE_CLK_MUX(timer10_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L4PER_TIMER10_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer11_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L4PER_TIMER11_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer1_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer2_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L4PER_TIMER2_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer3_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L4PER_TIMER3_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer4_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L4PER_TIMER4_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *timer5_gfclk_mux_parents[] = {
+ "dss_syc_gfclk_div", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(timer5_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_TIMER5_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer6_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_TIMER6_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer7_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_TIMER7_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer8_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_TIMER8_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer9_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L4PER_TIMER9_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+/* Leaf clocks controlled by modules */
+
+static const char *dss_32khz_clk_parents[] = {
+ "sys_32k_ck",
+};
+
+static struct clk dss_32khz_clk;
+
+static const struct clk_ops dss_32khz_clk_ops = {
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .init = &omap2_init_clk_clkdm,
+};
+
+static struct clk_hw_omap dss_32khz_clk_hw = {
+ .hw = {
+ .clk = &dss_32khz_clk,
+ },
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP54XX_CM_DSS_DSS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(dss_32khz_clk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static const char *dss_48mhz_clk_parents[] = {
+ "func_48m_fclk",
+};
+
+static struct clk dss_48mhz_clk;
+
+static struct clk_hw_omap dss_48mhz_clk_hw = {
+ .hw = {
+ .clk = &dss_48mhz_clk,
+ },
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP54XX_CM_DSS_DSS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(dss_48mhz_clk, dss_48mhz_clk_parents, dss_32khz_clk_ops);
+
+static const char *dss_dss_clk_parents[] = {
+ "dpll_per_h12x2_ck",
+};
+
+static struct clk dss_dss_clk;
+
+static struct clk_hw_omap dss_dss_clk_hw = {
+ .hw = {
+ .clk = &dss_dss_clk,
+ },
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP54XX_CM_DSS_DSS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(dss_dss_clk, dss_dss_clk_parents, dss_32khz_clk_ops);
+
+static const char *dss_sys_clk_parents[] = {
+ "dss_syc_gfclk_div",
+};
+
+static struct clk dss_sys_clk;
+
+static struct clk_hw_omap dss_sys_clk_hw = {
+ .hw = {
+ .clk = &dss_sys_clk,
+ },
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP54XX_CM_DSS_DSS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(dss_sys_clk, dss_sys_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio1_dbclk;
+
+static struct clk_hw_omap gpio1_dbclk_hw = {
+ .hw = {
+ .clk = &gpio1_dbclk,
+ },
+ .clkdm_name = "wkupaon_clkdm",
+ .enable_reg = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio1_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio2_dbclk;
+
+static struct clk_hw_omap gpio2_dbclk_hw = {
+ .hw = {
+ .clk = &gpio2_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio2_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio3_dbclk;
+
+static struct clk_hw_omap gpio3_dbclk_hw = {
+ .hw = {
+ .clk = &gpio3_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio3_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio4_dbclk;
+
+static struct clk_hw_omap gpio4_dbclk_hw = {
+ .hw = {
+ .clk = &gpio4_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio4_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio5_dbclk;
+
+static struct clk_hw_omap gpio5_dbclk_hw = {
+ .hw = {
+ .clk = &gpio5_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio5_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio6_dbclk;
+
+static struct clk_hw_omap gpio6_dbclk_hw = {
+ .hw = {
+ .clk = &gpio6_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio6_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio7_dbclk;
+
+static struct clk_hw_omap gpio7_dbclk_hw = {
+ .hw = {
+ .clk = &gpio7_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio7_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk gpio8_dbclk;
+
+static struct clk_hw_omap gpio8_dbclk_hw = {
+ .hw = {
+ .clk = &gpio8_dbclk,
+ },
+ .clkdm_name = "l4per_clkdm",
+ .enable_reg = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(gpio8_dbclk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static const char *iss_ctrlclk_parents[] = {
+ "func_96m_fclk",
+};
+
+static struct clk iss_ctrlclk;
+
+static struct clk_hw_omap iss_ctrlclk_hw = {
+ .hw = {
+ .clk = &iss_ctrlclk,
+ },
+ .clkdm_name = "cam_clkdm",
+ .enable_reg = OMAP54XX_CM_CAM_ISS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(iss_ctrlclk, iss_ctrlclk_parents, dss_32khz_clk_ops);
+
+static const char *lli_txphy_clk_parents[] = {
+ "dpll_unipro1_clkdcoldo",
+};
+
+static struct clk lli_txphy_clk;
+
+static struct clk_hw_omap lli_txphy_clk_hw = {
+ .hw = {
+ .clk = &lli_txphy_clk,
+ },
+ .clkdm_name = "mipiext_clkdm",
+ .enable_reg = OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(lli_txphy_clk, lli_txphy_clk_parents, dss_32khz_clk_ops);
+
+static const char *lli_txphy_ls_clk_parents[] = {
+ "dpll_unipro1_m2_ck",
+};
+
+static struct clk lli_txphy_ls_clk;
+
+static struct clk_hw_omap lli_txphy_ls_clk_hw = {
+ .hw = {
+ .clk = &lli_txphy_ls_clk,
+ },
+ .clkdm_name = "mipiext_clkdm",
+ .enable_reg = OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(lli_txphy_ls_clk, lli_txphy_ls_clk_parents,
+ dss_32khz_clk_ops);
+
+static struct clk mmc1_32khz_clk;
+
+static struct clk_hw_omap mmc1_32khz_clk_hw = {
+ .hw = {
+ .clk = &mmc1_32khz_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(mmc1_32khz_clk, dss_32khz_clk_parents, dss_32khz_clk_ops);
+
+static struct clk sata_ref_clk;
+
+static struct clk_hw_omap sata_ref_clk_hw = {
+ .hw = {
+ .clk = &sata_ref_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_SATA_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(sata_ref_clk, dss_syc_gfclk_div_parents, dss_32khz_clk_ops);
+
+static const char *slimbus1_slimbus_clk_parents[] = {
+ "slimbus_clk",
+};
+
+static struct clk slimbus1_slimbus_clk;
+
+static struct clk_hw_omap slimbus1_slimbus_clk_hw = {
+ .hw = {
+ .clk = &slimbus1_slimbus_clk,
+ },
+ .clkdm_name = "abe_clkdm",
+ .enable_reg = OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(slimbus1_slimbus_clk, slimbus1_slimbus_clk_parents,
+ dss_32khz_clk_ops);
+
+static const char *usb_host_hs_hsic480m_p1_clk_parents[] = {
+ "dpll_usb_m2_ck",
+};
+
+static struct clk usb_host_hs_hsic480m_p1_clk;
+
+static struct clk_hw_omap usb_host_hs_hsic480m_p1_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_hsic480m_p1_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_hsic480m_p1_clk,
+ usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops);
+
+static struct clk usb_host_hs_hsic480m_p2_clk;
+
+static struct clk_hw_omap usb_host_hs_hsic480m_p2_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_hsic480m_p2_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_hsic480m_p2_clk,
+ usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops);
+
+static struct clk usb_host_hs_hsic480m_p3_clk;
+
+static struct clk_hw_omap usb_host_hs_hsic480m_p3_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_hsic480m_p3_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_hsic480m_p3_clk,
+ usb_host_hs_hsic480m_p1_clk_parents, dss_32khz_clk_ops);
+
+static const char *usb_host_hs_hsic60m_p1_clk_parents[] = {
+ "l3init_60m_fclk",
+};
+
+static struct clk usb_host_hs_hsic60m_p1_clk;
+
+static struct clk_hw_omap usb_host_hs_hsic60m_p1_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_hsic60m_p1_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_hsic60m_p1_clk,
+ usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops);
+
+static struct clk usb_host_hs_hsic60m_p2_clk;
+
+static struct clk_hw_omap usb_host_hs_hsic60m_p2_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_hsic60m_p2_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_hsic60m_p2_clk,
+ usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops);
+
+static struct clk usb_host_hs_hsic60m_p3_clk;
+
+static struct clk_hw_omap usb_host_hs_hsic60m_p3_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_hsic60m_p3_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_hsic60m_p3_clk,
+ usb_host_hs_hsic60m_p1_clk_parents, dss_32khz_clk_ops);
+
+static const char *utmi_p1_gfclk_parents[] = {
+ "l3init_60m_fclk", "xclk60mhsp1",
+};
+
+DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ OMAP54XX_CLKSEL_UTMI_P1_SHIFT, OMAP54XX_CLKSEL_UTMI_P1_WIDTH,
+ 0x0, NULL);
+
+static const char *usb_host_hs_utmi_p1_clk_parents[] = {
+ "utmi_p1_gfclk",
+};
+
+static struct clk usb_host_hs_utmi_p1_clk;
+
+static struct clk_hw_omap usb_host_hs_utmi_p1_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_utmi_p1_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_utmi_p1_clk, usb_host_hs_utmi_p1_clk_parents,
+ dss_32khz_clk_ops);
+
+static const char *utmi_p2_gfclk_parents[] = {
+ "l3init_60m_fclk", "xclk60mhsp2",
+};
+
+DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ OMAP54XX_CLKSEL_UTMI_P2_SHIFT, OMAP54XX_CLKSEL_UTMI_P2_WIDTH,
+ 0x0, NULL);
+
+static const char *usb_host_hs_utmi_p2_clk_parents[] = {
+ "utmi_p2_gfclk",
+};
+
+static struct clk usb_host_hs_utmi_p2_clk;
+
+static struct clk_hw_omap usb_host_hs_utmi_p2_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_utmi_p2_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_utmi_p2_clk, usb_host_hs_utmi_p2_clk_parents,
+ dss_32khz_clk_ops);
+
+static struct clk usb_host_hs_utmi_p3_clk;
+
+static struct clk_hw_omap usb_host_hs_utmi_p3_clk_hw = {
+ .hw = {
+ .clk = &usb_host_hs_utmi_p3_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_host_hs_utmi_p3_clk, usb_host_hs_hsic60m_p1_clk_parents,
+ dss_32khz_clk_ops);
+
+static const char *usb_otg_ss_refclk960m_parents[] = {
+ "dpll_usb_clkdcoldo",
+};
+
+static struct clk usb_otg_ss_refclk960m;
+
+static struct clk_hw_omap usb_otg_ss_refclk960m_hw = {
+ .hw = {
+ .clk = &usb_otg_ss_refclk960m,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_otg_ss_refclk960m, usb_otg_ss_refclk960m_parents,
+ dss_32khz_clk_ops);
+
+static struct clk usb_tll_hs_usb_ch0_clk;
+
+static struct clk_hw_omap usb_tll_hs_usb_ch0_clk_hw = {
+ .hw = {
+ .clk = &usb_tll_hs_usb_ch0_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_tll_hs_usb_ch0_clk, usb_host_hs_hsic60m_p1_clk_parents,
+ dss_32khz_clk_ops);
+
+static struct clk usb_tll_hs_usb_ch1_clk;
+
+static struct clk_hw_omap usb_tll_hs_usb_ch1_clk_hw = {
+ .hw = {
+ .clk = &usb_tll_hs_usb_ch1_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_tll_hs_usb_ch1_clk, usb_host_hs_hsic60m_p1_clk_parents,
+ dss_32khz_clk_ops);
+
+static struct clk usb_tll_hs_usb_ch2_clk;
+
+static struct clk_hw_omap usb_tll_hs_usb_ch2_clk_hw = {
+ .hw = {
+ .clk = &usb_tll_hs_usb_ch2_clk,
+ },
+ .clkdm_name = "l3init_clkdm",
+ .enable_reg = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL,
+ .enable_bit = OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT,
+};
+
+DEFINE_STRUCT_CLK(usb_tll_hs_usb_ch2_clk, usb_host_hs_hsic60m_p1_clk_parents,
+ dss_32khz_clk_ops);
+
+/* Remaining optional clocks */
+DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
+ OMAP54XX_CM_ABE_AESS_CLKCTRL,
+ OMAP54XX_CLKSEL_AESS_FCLK_SHIFT,
+ OMAP54XX_CLKSEL_AESS_FCLK_WIDTH, 0x0, NULL);
+
+static const char *dmic_sync_mux_ck_parents[] = {
+ "abe_24m_fclk", "dss_syc_gfclk_div", "func_24m_clk",
+};
+
+DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_DMIC_CLKCTRL,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+
+static const char *dmic_gfclk_parents[] = {
+ "dmic_sync_mux_ck", "pad_clks", "slimbus_clk",
+};
+
+DEFINE_CLK_MUX(dmic_gfclk, dmic_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_DMIC_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(fdif_fclk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, 0x0,
+ OMAP54XX_CM_CAM_FDIF_CLKCTRL, OMAP54XX_CLKSEL_FCLK_SHIFT,
+ OMAP54XX_CLKSEL_FCLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(hsi_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
+ OMAP54XX_CM_L3INIT_HSI_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
+ OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCASP_CLKCTRL,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+
+static const char *mcasp_gfclk_parents[] = {
+ "mcasp_sync_mux_ck", "pad_clks", "slimbus_clk",
+};
+
+DEFINE_CLK_MUX(mcasp_gfclk, mcasp_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCASP_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCBSP1_CLKCTRL,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+
+static const char *mcbsp1_gfclk_parents[] = {
+ "mcbsp1_sync_mux_ck", "pad_clks", "slimbus_clk",
+};
+
+DEFINE_CLK_MUX(mcbsp1_gfclk, mcbsp1_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCBSP1_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCBSP2_CLKCTRL,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+
+static const char *mcbsp2_gfclk_parents[] = {
+ "mcbsp2_sync_mux_ck", "pad_clks", "slimbus_clk",
+};
+
+DEFINE_CLK_MUX(mcbsp2_gfclk, mcbsp2_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCBSP2_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCBSP3_CLKCTRL,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+
+static const char *mcbsp3_gfclk_parents[] = {
+ "mcbsp3_sync_mux_ck", "pad_clks", "slimbus_clk",
+};
+
+DEFINE_CLK_MUX(mcbsp3_gfclk, mcbsp3_gfclk_parents, NULL, 0x0,
+ OMAP54XX_CM_ABE_MCBSP3_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+static const char *mmc1_fclk_mux_parents[] = {
+ "func_128m_clk", "dpll_per_m2x2_ck",
+};
+
+DEFINE_CLK_MUX(mmc1_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L3INIT_MMC1_CLKCTRL,
+ OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc1_fclk, "mmc1_fclk_mux", &mmc1_fclk_mux, 0x0,
+ OMAP54XX_CM_L3INIT_MMC1_CLKCTRL, OMAP54XX_CLKSEL_DIV_SHIFT,
+ OMAP54XX_CLKSEL_DIV_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mmc2_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
+ OMAP54XX_CM_L3INIT_MMC2_CLKCTRL,
+ OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT,
+ OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc2_fclk, "mmc2_fclk_mux", &mmc2_fclk_mux, 0x0,
+ OMAP54XX_CM_L3INIT_MMC2_CLKCTRL, OMAP54XX_CLKSEL_DIV_SHIFT,
+ OMAP54XX_CLKSEL_DIV_WIDTH, 0x0, NULL);
+
+/* SCRM aux clk nodes */
+
+static const struct clksel auxclk_src_sel[] = {
+ { .parent = &sys_clkin, .rates = div_1_0_rates },
+ { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+ { .parent = NULL },
+};
+
+static const char *auxclk_src_ck_parents[] = {
+ "sys_clkin", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
+};
+
+static const struct clk_ops auxclk_src_ck_ops = {
+ .enable = &omap2_dflt_clk_enable,
+ .disable = &omap2_dflt_clk_disable,
+ .is_enabled = &omap2_dflt_clk_is_enabled,
+ .recalc_rate = &omap2_clksel_recalc,
+ .get_parent = &omap2_clksel_find_parent_index,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
+ OMAP5_SCRM_AUXCLK0, OMAP5_SRCSELECT_MASK,
+ OMAP5_SCRM_AUXCLK0, OMAP5_ENABLE_SHIFT, NULL,
+ auxclk_src_ck_parents, auxclk_src_ck_ops);
+
+DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
+ OMAP5_SCRM_AUXCLK0, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
+ 0x0, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
+ OMAP5_SCRM_AUXCLK1, OMAP5_SRCSELECT_MASK,
+ OMAP5_SCRM_AUXCLK1, OMAP5_ENABLE_SHIFT, NULL,
+ auxclk_src_ck_parents, auxclk_src_ck_ops);
+
+DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
+ OMAP5_SCRM_AUXCLK1, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
+ 0x0, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
+ OMAP5_SCRM_AUXCLK2, OMAP5_SRCSELECT_MASK,
+ OMAP5_SCRM_AUXCLK2, OMAP5_ENABLE_SHIFT, NULL,
+ auxclk_src_ck_parents, auxclk_src_ck_ops);
+
+DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
+ OMAP5_SCRM_AUXCLK2, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
+ 0x0, NULL);
+
+DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
+ OMAP5_SCRM_AUXCLK3, OMAP5_SRCSELECT_MASK,
+ OMAP5_SCRM_AUXCLK3, OMAP5_ENABLE_SHIFT, NULL,
+ auxclk_src_ck_parents, auxclk_src_ck_ops);
+
+DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
+ OMAP5_SCRM_AUXCLK3, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
+ 0x0, NULL);
+
+static const char *auxclkreq_ck_parents[] = {
+ "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
+ "auxclk5_ck",
+};
+
+DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
+ OMAP5_SCRM_AUXCLKREQ0, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
+ 0x0, NULL);
+
+DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
+ OMAP5_SCRM_AUXCLKREQ1, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
+ 0x0, NULL);
+
+DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
+ OMAP5_SCRM_AUXCLKREQ2, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
+ 0x0, NULL);
+
+DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
+ OMAP5_SCRM_AUXCLKREQ3, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
+ 0x0, NULL);
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk omap54xx_clks[] = {
+ CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_54XX),
+ CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_54XX),
+ CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_54XX),
+ CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_54XX),
+ CLK(NULL, "slimbus_clk", &slimbus_clk, CK_54XX),
+ CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_54XX),
+ CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_54XX),
+ CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_54XX),
+ CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_54XX),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_54XX),
+ CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_54XX),
+ CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_54XX),
+ CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_54XX),
+ CLK(NULL, "sys_clkin", &sys_clkin, CK_54XX),
+ CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_54XX),
+ CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_54XX),
+ CLK(NULL, "abe_dpll_bypass_clk_mux", &abe_dpll_bypass_clk_mux, CK_54XX),
+ CLK(NULL, "abe_dpll_clk_mux", &abe_dpll_clk_mux, CK_54XX),
+ CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_54XX),
+ CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_54XX),
+ CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_54XX),
+ CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_54XX),
+ CLK(NULL, "abe_clk", &abe_clk, CK_54XX),
+ CLK(NULL, "abe_iclk", &abe_iclk, CK_54XX),
+ CLK(NULL, "abe_lp_clk_div", &abe_lp_clk_div, CK_54XX),
+ CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_54XX),
+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h21x2_ck", &dpll_core_h21x2_ck, CK_54XX),
+ CLK(NULL, "c2c_fclk", &c2c_fclk, CK_54XX),
+ CLK(NULL, "c2c_iclk", &c2c_iclk, CK_54XX),
+ CLK(NULL, "custefuse_sys_gfclk_div", &custefuse_sys_gfclk_div, CK_54XX),
+ CLK(NULL, "dpll_core_h11x2_ck", &dpll_core_h11x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h12x2_ck", &dpll_core_h12x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h13x2_ck", &dpll_core_h13x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h14x2_ck", &dpll_core_h14x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h22x2_ck", &dpll_core_h22x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h23x2_ck", &dpll_core_h23x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_h24x2_ck", &dpll_core_h24x2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_54XX),
+ CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_54XX),
+ CLK(NULL, "iva_dpll_hs_clk_div", &iva_dpll_hs_clk_div, CK_54XX),
+ CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_54XX),
+ CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_54XX),
+ CLK(NULL, "dpll_iva_h11x2_ck", &dpll_iva_h11x2_ck, CK_54XX),
+ CLK(NULL, "dpll_iva_h12x2_ck", &dpll_iva_h12x2_ck, CK_54XX),
+ CLK(NULL, "mpu_dpll_hs_clk_div", &mpu_dpll_hs_clk_div, CK_54XX),
+ CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_54XX),
+ CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_54XX),
+ CLK(NULL, "per_dpll_hs_clk_div", &per_dpll_hs_clk_div, CK_54XX),
+ CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_54XX),
+ CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_54XX),
+ CLK(NULL, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, CK_54XX),
+ CLK(NULL, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, CK_54XX),
+ CLK(NULL, "dpll_per_h14x2_ck", &dpll_per_h14x2_ck, CK_54XX),
+ CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_54XX),
+ CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_54XX),
+ CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_54XX),
+ CLK(NULL, "dpll_unipro1_ck", &dpll_unipro1_ck, CK_54XX),
+ CLK(NULL, "dpll_unipro1_clkdcoldo", &dpll_unipro1_clkdcoldo, CK_54XX),
+ CLK(NULL, "dpll_unipro1_m2_ck", &dpll_unipro1_m2_ck, CK_54XX),
+ CLK(NULL, "dpll_unipro2_ck", &dpll_unipro2_ck, CK_54XX),
+ CLK(NULL, "dpll_unipro2_clkdcoldo", &dpll_unipro2_clkdcoldo, CK_54XX),
+ CLK(NULL, "dpll_unipro2_m2_ck", &dpll_unipro2_m2_ck, CK_54XX),
+ CLK(NULL, "usb_dpll_hs_clk_div", &usb_dpll_hs_clk_div, CK_54XX),
+ CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_54XX),
+ CLK(NULL, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, CK_54XX),
+ CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_54XX),
+ CLK(NULL, "dss_syc_gfclk_div", &dss_syc_gfclk_div, CK_54XX),
+ CLK(NULL, "l3_iclk_div", &l3_iclk_div, CK_54XX),
+ CLK(NULL, "func_128m_clk", &func_128m_clk, CK_54XX),
+ CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_54XX),
+ CLK(NULL, "func_24m_clk", &func_24m_clk, CK_54XX),
+ CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_54XX),
+ CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_54XX),
+ CLK(NULL, "gpu_core_gclk_mux", &gpu_core_gclk_mux, CK_54XX),
+ CLK(NULL, "gpu_hyd_gclk_mux", &gpu_hyd_gclk_mux, CK_54XX),
+ CLK(NULL, "gpu_l3_iclk", &gpu_l3_iclk, CK_54XX),
+ CLK(NULL, "l3init_60m_fclk", &l3init_60m_fclk, CK_54XX),
+ CLK(NULL, "wkupaon_iclk_mux", &wkupaon_iclk_mux, CK_54XX),
+ CLK(NULL, "l3instr_ts_gclk_div", &l3instr_ts_gclk_div, CK_54XX),
+ CLK(NULL, "l4_root_clk_div", &l4_root_clk_div, CK_54XX),
+ CLK(NULL, "timer10_gfclk_mux", &timer10_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer11_gfclk_mux", &timer11_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer1_gfclk_mux", &timer1_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer2_gfclk_mux", &timer2_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer3_gfclk_mux", &timer3_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer4_gfclk_mux", &timer4_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer5_gfclk_mux", &timer5_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer6_gfclk_mux", &timer6_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer7_gfclk_mux", &timer7_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer8_gfclk_mux", &timer8_gfclk_mux, CK_54XX),
+ CLK(NULL, "timer9_gfclk_mux", &timer9_gfclk_mux, CK_54XX),
+ CLK(NULL, "dss_32khz_clk", &dss_32khz_clk, CK_54XX),
+ CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_54XX),
+ CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_54XX),
+ CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_54XX),
+ CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_54XX),
+ CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_54XX),
+ CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_54XX),
+ CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_54XX),
+ CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_54XX),
+ CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_54XX),
+ CLK(NULL, "gpio7_dbclk", &gpio7_dbclk, CK_54XX),
+ CLK(NULL, "gpio8_dbclk", &gpio8_dbclk, CK_54XX),
+ CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_54XX),
+ CLK(NULL, "lli_txphy_clk", &lli_txphy_clk, CK_54XX),
+ CLK(NULL, "lli_txphy_ls_clk", &lli_txphy_ls_clk, CK_54XX),
+ CLK(NULL, "mmc1_32khz_clk", &mmc1_32khz_clk, CK_54XX),
+ CLK(NULL, "sata_ref_clk", &sata_ref_clk, CK_54XX),
+ CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_hsic480m_p3_clk", &usb_host_hs_hsic480m_p3_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_hsic60m_p3_clk", &usb_host_hs_hsic60m_p3_clk, CK_54XX),
+ CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_54XX),
+ CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_54XX),
+ CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_54XX),
+ CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_54XX),
+ CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_54XX),
+ CLK(NULL, "usb_otg_ss_refclk960m", &usb_otg_ss_refclk960m, CK_54XX),
+ CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_54XX),
+ CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_54XX),
+ CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_54XX),
+ CLK(NULL, "aess_fclk", &aess_fclk, CK_54XX),
+ CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_54XX),
+ CLK(NULL, "dmic_gfclk", &dmic_gfclk, CK_54XX),
+ CLK(NULL, "fdif_fclk", &fdif_fclk, CK_54XX),
+ CLK(NULL, "hsi_fclk", &hsi_fclk, CK_54XX),
+ CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_54XX),
+ CLK(NULL, "mcasp_gfclk", &mcasp_gfclk, CK_54XX),
+ CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_54XX),
+ CLK(NULL, "mcbsp1_gfclk", &mcbsp1_gfclk, CK_54XX),
+ CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_54XX),
+ CLK(NULL, "mcbsp2_gfclk", &mcbsp2_gfclk, CK_54XX),
+ CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_54XX),
+ CLK(NULL, "mcbsp3_gfclk", &mcbsp3_gfclk, CK_54XX),
+ CLK(NULL, "mmc1_fclk_mux", &mmc1_fclk_mux, CK_54XX),
+ CLK(NULL, "mmc1_fclk", &mmc1_fclk, CK_54XX),
+ CLK(NULL, "mmc2_fclk_mux", &mmc2_fclk_mux, CK_54XX),
+ CLK(NULL, "mmc2_fclk", &mmc2_fclk, CK_54XX),
+ CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_54XX),
+ CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_54XX),
+ CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_54XX),
+ CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_54XX),
+ CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_54XX),
+ CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_54XX),
+ CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_54XX),
+ CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_54XX),
+ CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_54XX),
+ CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_54XX),
+ CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_54XX),
+ CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_54XX),
+ CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_54XX),
+ CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_54XX),
+ CLK(NULL, "gpmc_ck", &dummy_ck, CK_54XX),
+ CLK("omap_i2c.1", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_i2c.2", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_i2c.3", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_i2c.4", "ick", &dummy_ck, CK_54XX),
+ CLK(NULL, "mailboxes_ick", &dummy_ck, CK_54XX),
+ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_54XX),
+ CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_54XX),
+ CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_54XX),
+ CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_54XX),
+ CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_54XX),
+ CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_54XX),
+ CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_54XX),
+ CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_54XX),
+ CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_54XX),
+ CLK(NULL, "uart1_ick", &dummy_ck, CK_54XX),
+ CLK(NULL, "uart2_ick", &dummy_ck, CK_54XX),
+ CLK(NULL, "uart3_ick", &dummy_ck, CK_54XX),
+ CLK(NULL, "uart4_ick", &dummy_ck, CK_54XX),
+ CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_54XX),
+ CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_54XX),
+ CLK("omap_wdt", "ick", &dummy_ck, CK_54XX),
+ CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_54XX),
+ CLK("omap_timer.1", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.2", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.3", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.4", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.9", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.10", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.11", "sys_ck", &sys_clkin, CK_54XX),
+ CLK("omap_timer.5", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
+ CLK("omap_timer.6", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
+ CLK("omap_timer.7", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
+ CLK("omap_timer.8", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
+};
+
+int __init omap5xxx_clk_init(void)
+{
+ u32 cpu_clkflg;
+ struct omap_clk *c;
+
+ if (soc_is_omap54xx()) {
+ cpu_mask = RATE_IN_54XX;
+ cpu_clkflg = CK_54XX;
+ }
+
+ /*
+ * Must stay commented until all OMAP SoC drivers are
+ * converted to runtime PM, or drivers may start crashing
+ *
+ * omap2_clk_disable_clkdm_control();
+ */
+
+ for (c = omap54xx_clks; c < omap54xx_clks + ARRAY_SIZE(omap54xx_clks);
+ c++) {
+ if (c->cpu & cpu_clkflg) {
+ clkdev_add(&c->lk);
+ if (!__clk_init(NULL, c->lk.clk))
+ omap2_init_clk_hw_omap_clocks(c->lk.clk);
+ }
+ }
+
+ omap2_clk_disable_autoidle_all();
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b402048..836311f 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -48,6 +48,7 @@ struct omap_clk {
#define CK_TI816X (1 << 7)
#define CK_446X (1 << 8)
#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
+#define CK_54XX (1 << 10) /* OMAP54xx specific clocks */
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
@@ -107,13 +108,31 @@ struct clockdomain;
}; \
DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
+
+#define DEFINE_CLK_OMAP_HSDIVIDER63(_name, _parent_name, \
+ _parent_ptr, _flags, \
+ _clksel_reg, _clksel_mask) \
+ \
+ _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
+ _parent_ptr, _flags, \
+ _clksel_reg, _clksel_mask, 63)
+
#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
_parent_ptr, _flags, \
_clksel_reg, _clksel_mask) \
+ \
+ _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
+ _parent_ptr, _flags, \
+ _clksel_reg, _clksel_mask, 31)
+
+
+#define _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
+ _parent_ptr, _flags, \
+ _clksel_reg, _clksel_mask, mdiv)\
static const struct clksel _name##_div[] = { \
{ \
.parent = _parent_ptr, \
- .rates = div31_1to31_rates \
+ .rates = div##mdiv##_1to##mdiv##_rates \
}, \
{ .parent = NULL }, \
}; \
@@ -143,6 +162,7 @@ struct clockdomain;
#define RATE_IN_4460 (1 << 7)
#define RATE_IN_AM33XX (1 << 8)
#define RATE_IN_TI814X (1 << 9)
+#define RATE_IN_54XX (1 << 10)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -463,6 +483,7 @@ extern const struct clksel_rate div_1_2_rates[];
extern const struct clksel_rate div_1_3_rates[];
extern const struct clksel_rate div_1_4_rates[];
extern const struct clksel_rate div31_1to31_rates[];
+extern const struct clksel_rate div63_1to63_rates[];
extern int am33xx_clk_init(void);
diff --git a/arch/arm/mach-omap2/clock54xx.h b/arch/arm/mach-omap2/clock54xx.h
new file mode 100644
index 0000000..3b09134
--- /dev/null
+++ b/arch/arm/mach-omap2/clock54xx.h
@@ -0,0 +1,12 @@
+/*
+ * OMAP5 clock function prototypes and macros
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK54XX_H
+
+int omap5xxx_clk_init(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index ef4d21b..c918efb 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -49,7 +49,7 @@ const struct clksel_rate dsp_ick_rates[] = {
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
const struct clksel_rate div_1_0_rates[] = {
- { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+ { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
{ .div = 0 },
};
@@ -61,57 +61,124 @@ const struct clksel_rate div3_1to4_rates[] = {
};
const struct clksel_rate div_1_1_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
{ .div = 0 },
};
const struct clksel_rate div_1_2_rates[] = {
- { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+ { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
{ .div = 0 },
};
const struct clksel_rate div_1_3_rates[] = {
- { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+ { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
{ .div = 0 },
};
const struct clksel_rate div_1_4_rates[] = {
- { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+ { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
{ .div = 0 },
};
const struct clksel_rate div31_1to31_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
- { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 0 },
+};
+
+const struct clksel_rate div63_1to63_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_54XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_54XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_54XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_54XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_54XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_54XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_54XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_54XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_54XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_54XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_54XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_54XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_54XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_54XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_54XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_54XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_54XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_54XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_54XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_54XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_54XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_54XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_54XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_54XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_54XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_54XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_54XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_54XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_54XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_54XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_54XX },
+ { .div = 32, .val = 32, .flags = RATE_IN_54XX },
+ { .div = 33, .val = 33, .flags = RATE_IN_54XX },
+ { .div = 34, .val = 34, .flags = RATE_IN_54XX },
+ { .div = 35, .val = 35, .flags = RATE_IN_54XX },
+ { .div = 36, .val = 36, .flags = RATE_IN_54XX },
+ { .div = 37, .val = 37, .flags = RATE_IN_54XX },
+ { .div = 38, .val = 38, .flags = RATE_IN_54XX },
+ { .div = 39, .val = 39, .flags = RATE_IN_54XX },
+ { .div = 40, .val = 40, .flags = RATE_IN_54XX },
+ { .div = 41, .val = 41, .flags = RATE_IN_54XX },
+ { .div = 42, .val = 42, .flags = RATE_IN_54XX },
+ { .div = 43, .val = 43, .flags = RATE_IN_54XX },
+ { .div = 44, .val = 44, .flags = RATE_IN_54XX },
+ { .div = 45, .val = 45, .flags = RATE_IN_54XX },
+ { .div = 46, .val = 46, .flags = RATE_IN_54XX },
+ { .div = 47, .val = 47, .flags = RATE_IN_54XX },
+ { .div = 48, .val = 48, .flags = RATE_IN_54XX },
+ { .div = 49, .val = 49, .flags = RATE_IN_54XX },
+ { .div = 50, .val = 50, .flags = RATE_IN_54XX },
+ { .div = 51, .val = 51, .flags = RATE_IN_54XX },
+ { .div = 52, .val = 52, .flags = RATE_IN_54XX },
+ { .div = 53, .val = 53, .flags = RATE_IN_54XX },
+ { .div = 54, .val = 54, .flags = RATE_IN_54XX },
+ { .div = 55, .val = 55, .flags = RATE_IN_54XX },
+ { .div = 56, .val = 56, .flags = RATE_IN_54XX },
+ { .div = 57, .val = 57, .flags = RATE_IN_54XX },
+ { .div = 58, .val = 58, .flags = RATE_IN_54XX },
+ { .div = 59, .val = 59, .flags = RATE_IN_54XX },
+ { .div = 60, .val = 60, .flags = RATE_IN_54XX },
+ { .div = 61, .val = 61, .flags = RATE_IN_54XX },
+ { .div = 62, .val = 62, .flags = RATE_IN_54XX },
+ { .div = 63, .val = 63, .flags = RATE_IN_54XX },
{ .div = 0 },
};
