On Fri, Nov 02, 2012 at 10:42:04AM +0000, N, Mugunthan V wrote: > > I saw those posts. The CPSW ip version changes tracks the internal IP > changes and there is no possible way to track the offset changes. For > example CPTS sub module offsets in DM814x and AM335x are different > though the CPTS version is same in both IP versions. So keeping these > offset in DT will make the same driver works directly with DT changes > for future SoC. But the CPSW versions are different, and the offsets could be determined that way, couldn't they? The TRM for the DM814x does not even make the distinction among CPSW_SS, CPSW_PORT, CPSW_CPDMA, and so on. Instead, it places all of the registers into one space called CPSW_3G. So I agree with Benoit. Placing all of the offsets into DT seems like over-engineering to me, unless you know of TI's plans to release a new SoC with the same CPSW version but different register offsets. Thanks, Richard -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
