On Fri, Sep 21, 2012 at 05:09:56PM +0530, Poddar, Sourav wrote: > Hi Felipe, > > On Fri, Sep 21, 2012 at 4:30 PM, Felipe Balbi <balbi@xxxxxx> wrote: > > On Fri, Sep 21, 2012 at 03:52:56PM +0530, Shubhrajyoti D wrote: > >> Overrun also causes an internal flag to be set, which disables further > >> reception. Before the next frame can > >> be received, the MPU must: > >> • Reset the RX FIFO. > >> • clear the internal flag. > >> > >> In the uart mode a dummy read is needed. Add the same. > > > > Very nice patch but I think commit log can be a bit more verbose. > > > > Please make the problem a little clearer. Why do we even get that > > interrupt fired if BRK_ERROR_BITS aren't set ? > > > According to LSR registers, there are few other bits like RX_FIFO_E( atleast 1 > character in RX_FIFO or TX FIFO Empty), which might be the cause of an > interrupt. ? right. In that case, is it really correct to just return if BRK_ERROR_BITS aren't set ? IRQ line will not toggle and we just might end up with an IRQ storm, right ? -- balbi
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