On Thu, Sep 13, 2012 at 6:23 PM, Dave Martin <dave.martin@xxxxxxxxxx> wrote: > On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote: >> In processors like A15/A7 L2 cache is unified and integrated within the >> processor cache hierarchy, so that it is not considered an outer cache >> anymore. For processors like A15/A7 flush_cache_all() ends up cleaning >> all cache levels up to Level of Coherency (LoC) that includes >> the L2 unified cache. >> >> When a single CPU is suspended (CPU idle) a complete L2 clean is not >> required, so generic cpu_suspend code must clean the data cache using the >> newly introduced cache LoUIS function. >> >> The context and stack pointer (context pointer) are cleaned to main memory >> using cache area functions that operate on MVA and guarantee that the data >> is written back to main memory (perform cache cleaning up to the Point of >> Coherency - PoC) so that the processor can fetch the context when the MMU >> is off in the cpu_resume code path. >> >> outer_cache management remains unchanged. > > LoUIS matches the power domain affected by turning a single CPU off > on most (all?) current v7 SoCs where this matters, but only by coincidence. > There is no guarantee of that. > > The _louis() API is useful, because this is exactly what you need to to > I-/D-/TLB synchronisation in an SMP OS. Using it as preparation for > powering a CPU off feels like misuse, at least in theory. > > For powerdown, we would logically need a separate function, > flush_cache_cpu() or something, whose job is precisely to flush those > levels which will be affected by the power-down if that single CPU. > In the series, there is patch "[PATCH 3/6]" which adds an API which let you operate on a specific level. Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
