This patch series provides an update of a previous posting: http://www.spinics.net/lists/arm-kernel/msg169075.html Main changes: - Changed the new API to Level of Unification Inner Shareable (LoUIS) - Fixed a pointer bug in __cpu_suspend_save code update - Added patches to update __cpu_disable and __v7_setup to LoUIS API - Changed the v7 dcache level function to make it clean/invalidate a specific level instead of up to a certain level v7 ARM architecture introduced the concept of cache levels and relative control registers to manage them. Cache operations that operate on set/way require to define the cache level at which maintenance operations are carried out by using coprocessor registers. Processors like A7/A15 integrates a unified L2 that is part of the cache level hierarchy; this implies that cache operations operating on all levels also end up cleaning the L2 unified cache which is a very time consuming operation and it is not needed for some power-down operations like single CPU shutdown. For v7, flush_kern_all() cleans all the cache levels up to the Level of Coherency which includes L2 in it. This is suboptimal for code paths that end up shutting-down a single processor like CPU hotplug and CPU idle, where only per-CPU cache state (ie L1 integrated cache) has to be cleaned and invalidated. To fix this performance issue this patchset introduces cache LoUIS (Level of Unification Inner Shareable) maintenance operations in the kernel. A new cache operations pointer is added to cpu_cache_fns void (*flush_kern_cache_louis)(void); that allows to clean and invalidate all data cache levels up to the LoUIS and invalidate the instruction cache. This new API should provide a sufficiently optimized API to be used in generic C code in the kernel for power management operations on most v7 systems. For architecture versions previous to v7, flush_kern_cache_louis() falls back to flush_kern_all() leaving the current behaviour unchanged. In order to allow finer grain operations on cache levels, this series also defines an assembly stub for v7 that allows to clean and invalidate a specific data cache level and it is provided for completeness. For A9/A5 processors Level of Unification Inner Shareable and Level of Coherency are equivalent hence this patch should not affect current kernel behaviour in any way when run on A9/A5 based systems, but should nonetheless be thoroughly tested on them. Tested on: - OMAP4 (S2R, cpuidle and hotplug) - OMAP5 (out of tree code) (S2R, cpuidle and hotplug) - TC2 big.LITTLE testchip (out of tree code) (cpuidle, on both A7 and A15 clusters) Lorenzo Pieralisi (4): ARM: mm: define LoUIS API for cache maintenance ops ARM: mm: add v7 cache LoUIS API implementation ARM: kernel: update cpu_suspend code to use cache LoUIS operations ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API Santosh Shilimkar (2): ARM: mm: add v7 dcache level API ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API arch/arm/include/asm/cacheflush.h | 17 +++++++++++ arch/arm/kernel/smp.c | 5 +++- arch/arm/kernel/suspend.c | 17 ++++++++++- arch/arm/mm/cache-v7.S | 62 +++++++++++++++++++++++++++++++++++++-- arch/arm/mm/proc-macros.S | 7 ++++- arch/arm/mm/proc-v7.S | 2 +- 6 files changed, 103 insertions(+), 7 deletions(-) -- 1.7.12 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
