On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson@xxxxxx> wrote:
> Hi Santosh,
>
> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
>> This provides PL310 Level 2 Cache Controller Device Tree
>> support for OMAP4 based devices.
>>
>> Cc: Benoit Cousson <b-cousson@xxxxxx>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
>> ---
>> arch/arm/boot/dts/omap4.dtsi | 7 +++++++
>> arch/arm/mach-omap2/omap4-common.c | 6 +++++-
>> 2 files changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 6717c71..cf1efb6 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -36,6 +36,13 @@
>> };
>> };
>>
>
>> + L2: l2-cache-controller {
>
> The reg offset is missing: l2-cache-controller@48242000
>
>> + compatible = "arm,pl310-cache";
>> + reg = <0x48242000 0x1000>;
>> + cache-unified;
>> + cache-level = <2>;
>> + };
>> +
>
> In theory, the L2 cache should be referenced from the CPUs.
>
Agree.
> Here is the way it is done for mpc8541cdc.dts for example:
>
I will move it under CPU. Thanks
regards
Santosh
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