On Wed, May 09, 2012 at 02:20:28PM +0530, Shilimkar, Santosh wrote: > The only change done common code is clearing 'XN' bit for DRAM > region in page table entries. The other change of setting the DACR > register is done in ARMv7 specific code. Yes, XN is an ARMv6+ thing. Before ARMv5, it was implementation defined. Some implementations used the bit to mean "allow writes to update the cache". Other implementations labelled this bit as "should be zero" while others labelled it as "should be one". The upshot of this is, we know that having this bit as '1' means that all the CPUs we support today work. I would be _very_ concerned to change this bit to zero as we _really_ don't know how the pre-ARMv6 CPUs would react. The solution to this is pretty simple - if ARMv6+ needs a different base section mapping value, then we need to extract that from the code and pass in the base section mapping value. I'll sort out a patch later today for this. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
