Re: GPIO debounce problems on 3.2

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On Wed, 1 Feb 2012, NeilBrown wrote:

> On Tue, 31 Jan 2012 22:47:32 -0700 (MST) Paul Walmsley <paul@xxxxxxxxx> wrote:
> 
> > Let me also answer the question from the MPU's perspective.  Suppose the 
> > MPU powerdomain has entered a low power state.  That means that the MPU 
> > INTC -- part of the MPU powerdomain -- is also in a low power state. 
> 
> My TRM says - in section 12.3.1.3 Power Management
> 
>     The MPU subsystem INTC belongs to the CORE power domain.
> 
> This is:
> 
>       AM/DM37x Multimedia Device
>       Silicon Revision 1.x
>       Version N
> 
> Is it wrong, are you wrong, or am I confused?

Hmm.  Since section 3.3.2.1 "Power Domains" mentions this too, and refers 
to CORE_RST, I suspect you and the TRM are right.  

So, for the moment, let's strike that second paragraph that I wrote about 
MPU wakeups.  I need to doublecheck with some other sources about exactly 
where the MPU INTC's clock comes from when the MPU clockdomain is idle.


- Paul
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