On Tue, 31 Jan 2012 22:47:32 -0700 (MST) Paul Walmsley <paul@xxxxxxxxx> wrote:
> Let me also answer the question from the MPU's perspective. Suppose the
> MPU powerdomain has entered a low power state. That means that the MPU
> INTC -- part of the MPU powerdomain -- is also in a low power state.
My TRM says - in section 12.3.1.3 Power Management
The MPU subsystem INTC belongs to the CORE power domain.
This is:
AM/DM37x Multimedia Device
Silicon Revision 1.x
Version N
Is it wrong, are you wrong, or am I confused?
Thanks,
NeilBrown
So
> neither the MPU nor the MPU INTC are working: clocks are disabled, the
> voltage may be scaled down, etc. So even if an IP block elsewhere on the
> chip asserts an MPU interrupt, the MPU INTC won't notice it; it's
> non-functional at this point. So for the MPU to notice the interrupt, it
> has to first come out of its low-power state. That happens when some IP
> block asserts that SWAKEUP signal to the PRCM, which, if it's programmed
> correctly, will then bring the MPU powerdomain out of its low-power state,
> re-enable clocks, etc. At that point, the MPU INTC should notice the
> interrupt, and the kernel should take it from there.
>
>
> - Paul
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