On Sun, 2012-01-22 at 22:11 +1100, NeilBrown wrote: > This code disables the auto-idling of some clocks ... not entirely sure of > the details. > > So it seems that it isn't a low power state but rather some clock being > allowed to turn off which is the problem. > > I guess I could selective try denying idle on each clock domain until I find > the one that is the problem.. I also did some testing: Normally DISPC's SIDLEMODE is set to smart idle and MIDLEMODE to smart standby. Changing either of them to no idle or no standby (respectively) removes the sync lost problem. But I guess that doesn't tell much, except that the problem is some kind of idle/wakeup problem. Then I noticed that the DISPC's ENWAKEUP is not set. Setting ENWAKEUP (with SIDLEMODE/IDLEMODE in smart mode) also removes the problem. Again, my understanding of OMAP PM is rather limited, but could this be the problem? Something (core/L3/whatever) goes to idle mode and when DSS needs to fetch data or requires a clock, and DSS is not able to wake the other component up? Tomi
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