On Thu, 2011-12-01 at 11:23 -0700, Paul Walmsley wrote: > On Thu, 1 Dec 2011, Tomi Valkeinen wrote: > > > Why is it that the rate of DSS functional clock (dss_dss_clk on OMAP4) > > cannot be set, but we need to get the parent of the fck, and set the > > rate of that? The same is on OMAP3. > > > > From driver's perspective I think this only makes things more complex, > > as the driver is not interested in the parent, only about the dss fck. > > Yeah, I agree. We've talked about implementing rate changes that > percolate up to some higher point in the clock tree, but have never gotten > around to it due to other, higher priorities. And now the common clock > discussion has reduced the desire to do much OMAP-specific implementation > of this stuff. > > Another (related) problem is that the driver probably needs to know the > ranges of the possible values that can be set. That's true. The DSS driver has knowledge of the possible divider ranges that the parent clock can use. Not very neat. And note that the DSS driver needs to know about the possible dividers, not the clock freq range. We need to get quite exact pixel clocks, derived via some dividers, and we iterate through the dividers trying to find a divider set that produces a pixel clock that is close to the required one. Tomi
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