This patch adds HWMOD data for all the peripherals of AM335X.
Signed-off-by: Vaibhav Hiremath <hvaibhav@xxxxxx>
Signed-off-by: Rachna Patil <rachna@xxxxxx>
Signed-off-by: Afzal Mohammed <afzal@xxxxxx>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2474 ++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
2 files changed, 2475 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 0000000..b1a34ff
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,2474 @@
+/*
+ * Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/mcspi.h>
+
+#include "omap_hwmod_common_data.h"
+#include "control.h"
+#include "cm33xx.h"
+
+/* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod am33xx_mpu_hwmod;
+static struct omap_hwmod am33xx_l3slow_hwmod;
+static struct omap_hwmod am33xx_l4wkup_hwmod;
+static struct omap_hwmod am33xx_l4per_hwmod;
+static struct omap_hwmod am33xx_uart1_hwmod;
+static struct omap_hwmod am33xx_uart2_hwmod;
+static struct omap_hwmod am33xx_uart3_hwmod;
+static struct omap_hwmod am33xx_uart4_hwmod;
+static struct omap_hwmod am33xx_uart5_hwmod;
+static struct omap_hwmod am33xx_uart6_hwmod;
+static struct omap_hwmod am33xx_timer0_hwmod;
+static struct omap_hwmod am33xx_timer1_hwmod;
+static struct omap_hwmod am33xx_timer2_hwmod;
+static struct omap_hwmod am33xx_timer3_hwmod;
+static struct omap_hwmod am33xx_timer4_hwmod;
+static struct omap_hwmod am33xx_timer5_hwmod;
+static struct omap_hwmod am33xx_timer6_hwmod;
+static struct omap_hwmod am33xx_timer7_hwmod;
+static struct omap_hwmod am33xx_wd_timer1_hwmod;
+static struct omap_hwmod am33xx_cpgmac0_hwmod;
+static struct omap_hwmod am33xx_icss_hwmod;
+static struct omap_hwmod am33xx_ieee5000_hwmod;
+static struct omap_hwmod am33xx_tptc0_hwmod;
+static struct omap_hwmod am33xx_tptc1_hwmod;
+static struct omap_hwmod am33xx_tptc2_hwmod;
+static struct omap_hwmod am33xx_gpio0_hwmod;
+static struct omap_hwmod am33xx_gpio1_hwmod;
+static struct omap_hwmod am33xx_gpio2_hwmod;
+static struct omap_hwmod am33xx_gpio3_hwmod;
+static struct omap_hwmod am33xx_i2c1_hwmod;
+static struct omap_hwmod am33xx_i2c2_hwmod;
+static struct omap_hwmod am33xx_usbss_hwmod;
+static struct omap_hwmod am33xx_mmc0_hwmod;
+static struct omap_hwmod am33xx_mmc1_hwmod;
+static struct omap_hwmod am33xx_mmc2_hwmod;
+static struct omap_hwmod am33xx_spi0_hwmod;
+static struct omap_hwmod am33xx_spi1_hwmod;
+
+/*
+ * Interconnects hwmod structures
+ * hwmods that compose the global AM33XX OCP interconnect
+ */
+
+/* MPU -> L3_SLOW Peripheral interface */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
+ .master = &am33xx_mpu_hwmod,
+ .slave = &am33xx_l3slow_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* L3 SLOW -> L4_PER Peripheral interface */
+static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
+ .master = &am33xx_l3slow_hwmod,
+ .slave = &am33xx_l4per_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* L3 SLOW -> L4_WKUP Peripheral interface */
+static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
+ .master = &am33xx_l3slow_hwmod,
+ .slave = &am33xx_l4wkup_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
+ &am33xx_l3_slow__l4_per,
+ &am33xx_l3_slow__l4_wkup,
+};
+
+/* Slave interfaces on the L3_SLOW interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
+ &am33xx_mpu__l3_slow,
+};
+
+static struct omap_hwmod am33xx_l3slow_hwmod = {
+ .name = "l3_slow",
+ .class = &l3_hwmod_class,
+ .clkdm_name = "l3s_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .masters = am33xx_l3_slow_masters,
+ .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
+ .slaves = am33xx_l3_slow_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
+};
+
+/* L4 PER -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+ {
+ .pa_start = AM33XX_GPIO1_BASE,
+ .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_gpio1_hwmod,
+ .clk = "l4ls_fck",
+ .addr = am33xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> GPIO3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+ {
+ .pa_start = AM33XX_GPIO2_BASE,
+ .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_gpio2_hwmod,
+ .clk = "l4ls_fck",
+ .addr = am33xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> GPIO4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+ {
+ .pa_start = AM33XX_GPIO3_BASE,
+ .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_gpio3_hwmod,
+ .clk = "l4ls_fck",
+ .addr = am33xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Master interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
+ &am33xx_l4_per__gpio1,
+ &am33xx_l4_per__gpio2,
+ &am33xx_l4_per__gpio3,
+};
+/* Slave interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
+ &am33xx_l3_slow__l4_per,
+};
+
+static struct omap_hwmod am33xx_l4per_hwmod = {
+ .name = "l4_per",
+ .class = &l4_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .masters = am33xx_l4_per_masters,
+ .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
+ .slaves = am33xx_l4_per_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+ {
+ .pa_start = AM33XX_I2C0_BASE,
+ .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_i2c1_hwmod,
+ .addr = am33xx_i2c1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+ {
+ .pa_start = AM33XX_GPIO0_BASE,
+ .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_gpio0_hwmod,
+ .clk = "l4ls_fck",
+ .addr = am33xx_gpio0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
+ &am33xx_l4_wkup__gpio0,
+};
+/* Slave interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
+ &am33xx_l3_slow__l4_wkup,
+};
+
+static struct omap_hwmod am33xx_l4wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .masters = am33xx_l4_wkup_masters,
+ .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
+ .slaves = am33xx_l4_wkup_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
+};
+
+/* 'adc_tsc' class */
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+ .name = "adc_tsc",
+};
+
+/* adc_tsc */
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+ { .irq = AM33XX_IRQ_TSC },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+ .name = "adc_tsc",
+ .class = &am33xx_adc_tsc_hwmod_class,
+ .mpu_irqs = am33xx_adc_tsc_irqs,
+ .main_clk = "adc_tsc_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'aes' class */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+ .name = "aes",
+};
+
+/* aes0 */
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+ { .irq = AM33XX_IRQ_AESEIP36t0_S },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+ .name = "aes0",
+ .class = &am33xx_aes_hwmod_class,
+ .mpu_irqs = am33xx_aes0_irqs,
+ .main_clk = "aes0_fck",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'cefuse' class */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+ .name = "cefuse",
+};
+
+/* cefuse */
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+ .name = "cefuse",
+ .class = &am33xx_cefuse_hwmod_class,
+ .main_clk = "cefuse_fck",
+ .clkdm_name = "l4_cefuse_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'clkdiv32k' class */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+ .name = "clkdiv32k",
+};
+
+/* clkdiv32k */
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+ .name = "clkdiv32k",
+ .class = &am33xx_clkdiv32k_hwmod_class,
+ .main_clk = "clkdiv32k_fck",
+ .clkdm_name = "clk_24mhz_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+};
+
+/* 'control' class */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+ .name = "control",
+};
+
+/* control */
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+ { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+ .name = "control",
+ .class = &am33xx_control_hwmod_class,
+ .mpu_irqs = am33xx_control_irqs,
+ .main_clk = "control_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+};
+
+/* 'cpgmac0' class */
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+ .name = "cpgmac0",
+};
+
+/* cpgmac0 */
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+ .name = "cpgmac0",
+ .class = &am33xx_cpgmac0_hwmod_class,
+ .main_clk = "cpgmac0_fck",
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'dcan' class */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+ .name = "dcan",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+ { .irq = AM33XX_IRQ_DCAN0_0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+ .name = "dcan0",
+ .class = &am33xx_dcan_hwmod_class,
+ .mpu_irqs = am33xx_dcan0_irqs,
+ .main_clk = "dcan0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+ { .irq = AM33XX_IRQ_DCAN1_0 },
+ { .irq = -1 },
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+ .name = "dcan1",
+ .class = &am33xx_dcan_hwmod_class,
+ .mpu_irqs = am33xx_dcan1_irqs,
+ .main_clk = "dcan1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'debugss' class */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+ .name = "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod am33xx_debugss_hwmod = {
+ .name = "debugss",
+ .class = &am33xx_debugss_hwmod_class,
+ .main_clk = "debugss_fck",
+ .clkdm_name = "l3_aon_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'elm' class */
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+ .name = "elm",
+};
+
+/* elm */
+static struct omap_hwmod am33xx_elm_hwmod = {
+ .name = "elm",
+ .class = &am33xx_elm_hwmod_class,
+ .main_clk = "elm_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'emif_fw' class */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+ .name = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+ .name = "emif_fw",
+ .class = &am33xx_emif_fw_hwmod_class,
+ .main_clk = "emif_fw_fck",
+ .clkdm_name = "l4fw_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
+};
+
+/* 'epwmss' class */
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+};
+
+/* epwmss0 */
+static struct omap_hwmod am33xx_epwmss0_hwmod = {
+ .name = "epwmss0",
+ .class = &am33xx_epwmss_hwmod_class,
+ .main_clk = "epwmss0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* epwmss1 */
+static struct omap_hwmod am33xx_epwmss1_hwmod = {
+ .name = "epwmss1",
+ .class = &am33xx_epwmss_hwmod_class,
+ .main_clk = "epwmss1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* epwmss2 */
+static struct omap_hwmod am33xx_epwmss2_hwmod = {
+ .name = "epwmss2",
+ .class = &am33xx_epwmss_hwmod_class,
+ .main_clk = "epwmss2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+/* 'gpio' class */
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &am33xx_gpio_sysc,
+ .rev = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+ { .irq = AM33XX_IRQ_GPIO0_1 },
+ { .irq = -1 },
+};
+
+/* gpio0 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
+ &am33xx_l4_wkup__gpio0,
+};
+
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+/* gpio0 */
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+ .name = "gpio1",
+ .class = &am33xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio0_irqs,
+ .main_clk = "gpio0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio0_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = am33xx_gpio0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+ { .irq = AM33XX_IRQ_GPIO1_1 },
+ { .irq = -1 },
+};
+
+/* gpio1 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
+ &am33xx_l4_per__gpio1,
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+ .name = "gpio2",
+ .class = &am33xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio1_irqs,
+ .main_clk = "gpio1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = am33xx_gpio1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+ { .irq = AM33XX_IRQ_GPIO2_1 },
+ { .irq = -1 },
+};
+
+/* gpio2 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
+ &am33xx_l4_per__gpio2,
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+/* gpio2 */
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+ .name = "gpio3",
+ .class = &am33xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio2_irqs,
+ .main_clk = "gpio2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = am33xx_gpio2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+ { .irq = AM33XX_IRQ_GPIO3_1 },
+ { .irq = -1 },
+};
+
+/* gpio3 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
+ &am33xx_l4_per__gpio3,
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+/* gpio3 */
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+ .name = "gpio4",
+ .class = &am33xx_gpio_hwmod_class,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = am33xx_gpio3_irqs,
+ .main_clk = "gpio3_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+ .slaves = am33xx_gpio3_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
+};
+
+/* 'gpmc' class */
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+};
+
+/* gpmc */
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &am33xx_gpmc_hwmod_class,
+ .main_clk = "gpmc_fck",
+ .clkdm_name = "l3s_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'i2c' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+static struct omap_hwmod_class i2c_class = {
+ .name = "i2c",
+ .sysc = &am33xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
+ .reset = &omap_i2c_reset,
+};
+
+/* I2C1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+ { .irq = AM33XX_IRQ_MSHSI2COCP0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
+ &am33xx_l4_wkup_i2c1,
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .mpu_irqs = i2c1_mpu_irqs,
+ .sdma_reqs = i2c1_edma_reqs,
+ .main_clk = "i2c1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .flags = HWMOD_16BIT_REG,
+ .dev_attr = &i2c_dev_attr,
+ .slaves = am33xx_i2c1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
+ .class = &i2c_class,
+};
+
+/* i2c2 */
+/* l4 per -> i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+ {
+ .pa_start = AM33XX_I2C1_BASE,
+ .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_i2c2_hwmod,
+ .addr = am33xx_i2c2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+ { .irq = AM33XX_IRQ_MSHSI2COCP1 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
+ &am335_l4_per_i2c2,
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .mpu_irqs = i2c2_mpu_irqs,
+ .sdma_reqs = i2c2_edma_reqs,
+ .main_clk = "i2c2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .flags = HWMOD_16BIT_REG,
+ .dev_attr = &i2c_dev_attr,
+ .slaves = am33xx_i2c2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
+ .class = &i2c_class,
+};
+
+/* 'icss' class */
+static struct omap_hwmod_class am33xx_icss_hwmod_class = {
+ .name = "icss",
+};
+
+/* icss */
+static struct omap_hwmod am33xx_icss_hwmod = {
+ .name = "icss",
+ .class = &am33xx_icss_hwmod_class,
+ .main_clk = "icss_fck",
+ .clkdm_name = "icss_ocp_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'ieee5000' class */
+static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
+ .name = "ieee5000",
+};
+
+/* ieee5000 */
+static struct omap_hwmod am33xx_ieee5000_hwmod = {
+ .name = "ieee5000",
+ .class = &am33xx_ieee5000_hwmod_class,
+ .main_clk = "ieee5000_fck",
+ .clkdm_name = "l3s_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/* 'l3' class */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+ .name = "l4_hs",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l4hs_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l3_main */
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &am33xx_l3_hwmod_class,
+ .clkdm_name = "l3_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'l4fw' class */
+static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
+ .name = "l4fw",
+};
+
+/* l4fw */
+static struct omap_hwmod am33xx_l4fw_hwmod = {
+ .name = "l4fw",
+ .class = &am33xx_l4fw_hwmod_class,
+ .clkdm_name = "l4fw_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'l4ls' class */
+static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
+ .name = "l4ls",
+};
+
+/* l4ls */
+static struct omap_hwmod am33xx_l4ls_hwmod = {
+ .name = "l4ls",
+ .class = &am33xx_l4ls_hwmod_class,
+ .main_clk = "l4ls_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'lcdc' class */
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+ .name = "lcdc",
+};
+
+/* lcdc */
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+ { .irq = AM33XX_IRQ_LCD },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+ .name = "lcdc",
+ .class = &am33xx_lcdc_hwmod_class,
+ .mpu_irqs = am33xx_lcdc_irqs,
+ .main_clk = "lcdc_fck",
+ .clkdm_name = "lcdc_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'mcasp' class */
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+ { .irq = 80 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+ .name = "mcasp0",
+ .class = &am33xx_mcasp_hwmod_class,
+ .mpu_irqs = am33xx_mcasp0_irqs,
+ .main_clk = "mcasp0_fck",
+ .clkdm_name = "l3s_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'mmc' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+ .rev_offs = 0x1fc,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+ { .irq = AM33XX_IRQ_MMCHS0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+ {
+ .pa_start = AM33XX_MMC0_BASE,
+ .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
+ .master = &am33xx_l4ls_hwmod,
+ .slave = &am33xx_mmc0_hwmod,
+ .clk = "mmc0_ick",
+ .addr = am33xx_mmc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
+ &am33xx_l4ls__mmc0,
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+ .name = "mmc1",
+ .class = &am33xx_mmc_hwmod_class,
+ .mpu_irqs = am33xx_mmc0_irqs,
+ .main_clk = "mmc0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc0_dev_attr,
+ .slaves = am33xx_mmc0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+ { .irq = AM33XX_IRQ_MMCHS1 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+ {
+ .pa_start = AM33XX_MMC1_BASE,
+ .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
+ .master = &am33xx_l4ls_hwmod,
+ .slave = &am33xx_mmc1_hwmod,
+ .clk = "mmc1_ick",
+ .addr = am33xx_mmc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
+ &am33xx_l4ls__mmc1,
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+ .name = "mmc2",
+ .class = &am33xx_mmc_hwmod_class,
+ .mpu_irqs = am33xx_mmc1_irqs,
+ .main_clk = "mmc1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc1_dev_attr,
+ .slaves = am33xx_mmc1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+ { .irq = AM33XX_IRQ_MMCHS2 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+ {
+ .pa_start = AM33XX_MMC2_BASE,
+ .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_mmc2_hwmod,
+ .clk = "mmc2_ick",
+ .addr = am33xx_mmc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
+ &am33xx_l3_main__mmc2,
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+ .name = "mmc3",
+ .class = &am33xx_mmc_hwmod_class,
+ .mpu_irqs = am33xx_mmc2_irqs,
+ .main_clk = "mmc2_fck",
+ .clkdm_name = "l3s_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &am33xx_mmc2_dev_attr,
+ .slaves = am33xx_mmc2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
+};
+
+/* Master interfaces on the MPU interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
+ &am33xx_mpu__l3_slow,
+};
+
+/* mpu */
+static struct omap_hwmod am33xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &mpu_hwmod_class,
+ .masters = am33xx_l3_mpu_masters,
+ .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .main_clk = "mpu_fck",
+ .clkdm_name = "mpu_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'ocmcram' class */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+ .name = "ocmcram",
+};
+
+/* ocmcram */
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+ .name = "ocmcram",
+ .class = &am33xx_ocmcram_hwmod_class,
+ .main_clk = "ocmcram_fck",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'ocpwp' class */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+ .name = "ocpwp",
+};
+
+/* ocpwp */
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+ .name = "ocpwp",
+ .class = &am33xx_ocpwp_hwmod_class,
+ .main_clk = "ocpwp_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'rtc' class */
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+ .name = "rtc",
+};
+
+/* rtc */
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+ { .irq = AM33XX_IRQ_RTC_TIMER },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+ .name = "rtc",
+ .class = &am33xx_rtc_hwmod_class,
+ .mpu_irqs = am33xx_rtc_irqs,
+ .main_clk = "rtc_fck",
+ .clkdm_name = "l4_rtc_clkdm",
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'sha0' class */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+ .name = "sha0",
+};
+
+/* sha0 */
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+ { .irq = AM33XX_IRQ_SHAEIP57t0_S },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+ .name = "sha0",
+ .class = &am33xx_sha0_hwmod_class,
+ .mpu_irqs = am33xx_sha0_irqs,
+ .main_clk = "sha0_fck",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+ { .irq = AM33XX_IRQ_SMARTREFLEX0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+ .name = "smartreflex0",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .mpu_irqs = am33xx_smartreflex0_irqs,
+ .main_clk = "smartreflex0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+ { .irq = AM33XX_IRQ_SMARTREFLEX1 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+ .name = "smartreflex1",
+ .class = &am33xx_smartreflex_hwmod_class,
+ .mpu_irqs = am33xx_smartreflex1_irqs,
+ .main_clk = "smartreflex1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'spi' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0110,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &am33xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+ { .irq = AM33XX_IRQ_MCSPIOCP0 },
+ { .irq = -1 },
+};
+
+struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+ {
+ .pa_start = AM33XX_SPI0_BASE,
+ .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { },
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_spi0_hwmod,
+ .clk = "spi0_ick",
+ .addr = am33xx_mcspi0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
+ &am33xx_l4_core__mcspi0,
+};
+
+struct omap2_mcspi_dev_attr mcspi_attrib = {
+ .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+ .name = "spi0",
+ .class = &am33xx_spi_hwmod_class,
+ .mpu_irqs = am33xx_spi0_irqs,
+ .main_clk = "spi0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+ .slaves = am33xx_mcspi0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+ { .irq = AM33XX_IRQ_SPI1 },
+ { .irq = -1 },
+};
+
+struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+ {
+ .pa_start = AM33XX_SPI1_BASE,
+ .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { },
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_spi1_hwmod,
+ .clk = "spi1_ick",
+ .addr = am33xx_mcspi1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
+ &am33xx_l4_core__mcspi1,
+};
+static struct omap_hwmod am33xx_spi1_hwmod = {
+ .name = "spi1",
+ .class = &am33xx_spi_hwmod_class,
+ .mpu_irqs = am33xx_spi1_irqs,
+ .main_clk = "spi1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi_attrib,
+ .slaves = am33xx_mcspi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
+};
+
+/* 'spinlock' class */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+};
+
+/* spinlock */
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &am33xx_spinlock_hwmod_class,
+ .main_clk = "spinlock_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'timer 0 & 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer_sysc,
+};
+
+/* timer0 */
+/* l4 wkup -> timer0 interface */
+static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER0_BASE,
+ .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_timer0_hwmod,
+ .clk = "timer0_ick",
+ .addr = am33xx_timer0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
+ &am33xx_l4wkup__timer0,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer0_hwmod = {
+ .name = "timer0",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer0_irqs,
+ .main_clk = "timer0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &am33xx_timer1ms_sysc,
+};
+
+/* l4 wkup -> timer1 interface */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER1_BASE,
+ .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_timer1_hwmod,
+ .clk = "timer1_ick",
+ .addr = am33xx_timer1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
+ &am33xx_l4wkup__timer1,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER1 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &am33xx_timer1ms_hwmod_class,
+ .mpu_irqs = am33xx_timer1_irqs,
+ .main_clk = "timer1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
+};
+
+/* timer2 */
+/* l4 per -> timer2 interface */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER2_BASE,
+ .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_timer2_hwmod,
+ .clk = "timer2_ick",
+ .addr = am33xx_timer2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
+ &am33xx_l4per__timer2,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER2 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer2_irqs,
+ .main_clk = "timer2_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
+ .clkdm_name = "l4ls_clkdm",
+};
+
+/* timer3 */
+/* l4 per -> timer3 interface */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER3_BASE,
+ .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_timer3_hwmod,
+ .clk = "timer3_ick",
+ .addr = am33xx_timer3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
+ &am33xx_l4per__timer3,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER3 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer3_irqs,
+ .main_clk = "timer3_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer3_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
+};
+
+/* timer4 */
+/* l4 per -> timer4 interface */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER4_BASE,
+ .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_timer4_hwmod,
+ .clk = "timer4_ick",
+ .addr = am33xx_timer4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
+ &am33xx_l4per__timer4,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER4 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer4_irqs,
+ .main_clk = "timer4_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer4_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
+ .clkdm_name = "l4ls_clkdm",
+};
+
+
+/* timer5 */
+/* l4 per -> timer5 interface */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER5_BASE,
+ .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_timer5_hwmod,
+ .clk = "timer5_ick",
+ .addr = am33xx_timer5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
+ &am33xx_l4per__timer5,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER5 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer5_irqs,
+ .main_clk = "timer5_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer5_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
+ .clkdm_name = "l4ls_clkdm",
+};
+
+/* timer6 */
+/* l4 per -> timer6 interface */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER6_BASE,
+ .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_timer6_hwmod,
+ .clk = "timer6_ick",
+ .addr = am33xx_timer6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
+ &am33xx_l4per__timer6,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER6 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer6_irqs,
+ .main_clk = "timer6_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer6_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
+ .clkdm_name = "l4ls_clkdm",
+};
+
+/* timer7 */
+/* l4 per -> timer7 interface */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+ {
+ .pa_start = AM33XX_TIMER7_BASE,
+ .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_timer7_hwmod,
+ .clk = "timer7_ick",
+ .addr = am33xx_timer7_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
+ &am33xx_l4per__timer7,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+ { .irq = AM33XX_IRQ_DMTIMER7 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &am33xx_timer_hwmod_class,
+ .mpu_irqs = am33xx_timer7_irqs,
+ .main_clk = "timer7_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_timer7_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
+ .clkdm_name = "l4ls_clkdm",
+};
+
+/* 'tpcc' class */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+/* tpcc */
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+ { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &am33xx_tpcc_hwmod_class,
+ .mpu_irqs = am33xx_tpcc_irqs,
+ .main_clk = "tpcc_ick",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+ .name = "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+ { .irq = AM33XX_IRQ_TPTC0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &am33xx_tptc_hwmod_class,
+ .mpu_irqs = am33xx_tptc0_irqs,
+ .main_clk = "tptc0_ick",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+ { .irq = AM33XX_IRQ_TPTC1 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &am33xx_tptc_hwmod_class,
+ .mpu_irqs = am33xx_tptc1_irqs,
+ .main_clk = "tptc1_ick",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+ { .irq = AM33XX_IRQ_TPTC2 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+ .name = "tptc2",
+ .class = &am33xx_tptc_hwmod_class,
+ .mpu_irqs = am33xx_tptc2_irqs,
+ .main_clk = "tptc2_ick",
+ .clkdm_name = "l3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+ .name = "uart",
+ .sysc = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+ { .name = "tx", .dma_req = 26, },
+ { .name = "rx", .dma_req = 27, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+ {
+ .pa_start = AM33XX_UART1_BASE,
+ .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_uart1_hwmod,
+ .clk = "uart1_ick",
+ .addr = am33xx_uart1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+ { .irq = AM33XX_IRQ_UART0 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
+ &am33xx_l4_wkup__uart1,
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &uart_class,
+ .mpu_irqs = am33xx_uart1_irqs,
+ .sdma_reqs = uart1_edma_reqs,
+ .main_clk = "uart1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_uart1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
+};
+
+/* uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+ {
+ .pa_start = AM33XX_UART2_BASE,
+ .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+ .slave = &am33xx_uart2_hwmod,
+ .clk = "uart2_ick",
+ .addr = am33xx_uart2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+ { .irq = AM33XX_IRQ_UART1 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
+ &am33xx_l4_ls__uart2,
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &uart_class,
+ .mpu_irqs = am33xx_uart2_irqs,
+ .main_clk = "uart2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .sdma_reqs = uart1_edma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_uart2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
+};
+
+/* uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+ {
+ .pa_start = AM33XX_UART3_BASE,
+ .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+ .slave = &am33xx_uart3_hwmod,
+ .clk = "uart3_ick",
+ .addr = am33xx_uart3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+ { .irq = AM33XX_IRQ_UART2 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
+ &am33xx_l4_ls__uart3,
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &uart_class,
+ .mpu_irqs = am33xx_uart3_irqs,
+ .main_clk = "uart3_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .sdma_reqs = uart1_edma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_uart3_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
+};
+
+/* uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+ {
+ .pa_start = AM33XX_UART4_BASE,
+ .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+ .slave = &am33xx_uart4_hwmod,
+ .clk = "uart4_ick",
+ .addr = am33xx_uart4_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+ { .irq = AM33XX_IRQ_UART3 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
+ &am33xx_l4_ls__uart4,
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &uart_class,
+ .mpu_irqs = am33xx_uart4_irqs,
+ .main_clk = "uart4_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .sdma_reqs = uart1_edma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_uart4_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
+};
+
+/* uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+ {
+ .pa_start = AM33XX_UART5_BASE,
+ .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+ .slave = &am33xx_uart5_hwmod,
+ .clk = "uart5_ick",
+ .addr = am33xx_uart5_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+ { .irq = AM33XX_IRQ_UART4 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
+ &am33xx_l4_ls__uart5,
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &uart_class,
+ .mpu_irqs = am33xx_uart5_irqs,
+ .main_clk = "uart5_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .sdma_reqs = uart1_edma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_uart5_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
+};
+
+/* uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+ {
+ .pa_start = AM33XX_UART6_BASE,
+ .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+ .slave = &am33xx_uart6_hwmod,
+ .clk = "uart6_ick",
+ .addr = am33xx_uart6_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+ { .irq = AM33XX_IRQ_UART5 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
+ &am33xx_l4_ls__uart6,
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &uart_class,
+ .mpu_irqs = am33xx_uart6_irqs,
+ .main_clk = "uart6_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .sdma_reqs = uart1_edma_reqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_uart6_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+};
+
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+ {
+ .pa_start = AM33XX_WDT1_BASE,
+ .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { },
+};
+
+/* l4_wkup -> wd_timer1 */
+static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_wd_timer1_hwmod,
+ .addr = am33xx_wd_timer1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* wd_timer1 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
+ &am33xx_l4wkup__wd_timer1,
+};
+
+/* wd_timer1 */
+/*
+ * TODO: device.c file uses hardcoded name for watchdog
+ timer driver "wd_timer2, so we are also using
+ same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+ .name = "wd_timer2",
+ .class = &am33xx_wd_timer_hwmod_class,
+ .main_clk = "wd_timer1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_wd_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
+};
+
+/* wdt0 */
+static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
+ { .irq = AM33XX_IRQ_WDT0 },
+ { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_wdt0_hwmod = {
+ .name = "wdt0",
+ .class = &am33xx_wd_timer_hwmod_class,
+ .mpu_irqs = am33xx_wdt0_irqs,
+ .main_clk = "wdt0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* 'wkup_m3' class */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+ .name = "wkup_m3",
+};
+
+/* wkup_m3 */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+ .name = "wkup_m3",
+ .class = &am33xx_wkup_m3_hwmod_class,
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .main_clk = "wkup_m3_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* L3 SLOW -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+ {
+ .name = "usbss",
+ .pa_start = AM33XX_USBSS_BASE,
+ .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb0",
+ .pa_start = AM33XX_USB0_BASE,
+ .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "musb1",
+ .pa_start = AM33XX_USB1_BASE,
+ .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+ .name = "usbotg",
+ .sysc = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+ { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
+ { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
+ { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
+ { .irq = -1, },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
+ .master = &am33xx_l3slow_hwmod,
+ .slave = &am33xx_usbss_hwmod,
+ .addr = am33xx_usbss_addr_space,
+ .user = OCP_USER_MPU,
+ .flags = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
+ &am33xx_l3_slow__usbss,
+};
+
+static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
+ { .role = "clkdcoldo", .clk = "usbotg_fck" },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+ .name = "usb_otg_hs",
+ .mpu_irqs = am33xx_usbss_mpu_irqs,
+ .main_clk = "usbotg_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = usbss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
+ .slaves = am33xx_usbss_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
+ .class = &am33xx_usbotg_class,
+};
+
+static __initdata struct omap_hwmod *am33xx_hwmods[] = {
+ /* l3 class */
+ &am33xx_l3_instr_hwmod,
+ &am33xx_l3_main_hwmod,
+ /* l3s class */
+ &am33xx_l3slow_hwmod,
+ /* l4hs class */
+ &am33xx_l4_hs_hwmod,
+ /* l4fw class */
+ &am33xx_l4fw_hwmod,
+ /* l4ls class */
+ &am33xx_l4ls_hwmod,
+ /* l4per class */
+ &am33xx_l4per_hwmod,
+ /* l4wkup class */
+ &am33xx_l4wkup_hwmod,
+
+ /* clkdiv32k class */
+ &am33xx_clkdiv32k_hwmod,
+ /* mpu class */
+ &am33xx_mpu_hwmod,
+ /* adc_tsc class */
+ &am33xx_adc_tsc_hwmod,
+ /* aes class */
+ &am33xx_aes0_hwmod,
+ /* cefuse class */
+ &am33xx_cefuse_hwmod,
+ /* control class */
+ &am33xx_control_hwmod,
+ /* dcan class */
+ &am33xx_dcan0_hwmod,
+ &am33xx_dcan1_hwmod,
+ /* debugss class */
+ &am33xx_debugss_hwmod,
+ /* elm class */
+ &am33xx_elm_hwmod,
+ /* emif_fw class */
+ &am33xx_emif_fw_hwmod,
+ /* epwmss class */
+ &am33xx_epwmss0_hwmod,
+ &am33xx_epwmss1_hwmod,
+ &am33xx_epwmss2_hwmod,
+ /* gpio class */
+ &am33xx_gpio0_hwmod,
+ &am33xx_gpio1_hwmod,
+ &am33xx_gpio2_hwmod,
+ &am33xx_gpio3_hwmod,
+ /* gpmc class */
+ &am33xx_gpmc_hwmod,
+ /* i2c class */
+ &am33xx_i2c1_hwmod,
+ &am33xx_i2c2_hwmod,
+ /* icss class */
+ &am33xx_icss_hwmod,
+ /* ieee5000 class */
+ &am33xx_ieee5000_hwmod,
+ /* mcasp class */
+ &am33xx_mcasp0_hwmod,
+ /* mmc class */
+ &am33xx_mmc0_hwmod,
+ &am33xx_mmc1_hwmod,
+ &am33xx_mmc2_hwmod,
+ /* ocmcram class */
+ &am33xx_ocmcram_hwmod,
+ /* ocpwp class */
+ &am33xx_ocpwp_hwmod,
+ /* rtc class */
+ &am33xx_rtc_hwmod,
+ /* sha0 class */
+ &am33xx_sha0_hwmod,
+ /* smartreflex class */
+ &am33xx_smartreflex0_hwmod,
+ &am33xx_smartreflex1_hwmod,
+ /* spi class */
+ &am33xx_spi0_hwmod,
+ &am33xx_spi1_hwmod,
+ /* spinlock class */
+ &am33xx_spinlock_hwmod,
+ /* uart class */
+ &am33xx_uart1_hwmod,
+ &am33xx_uart2_hwmod,
+ &am33xx_uart3_hwmod,
+ &am33xx_uart4_hwmod,
+ &am33xx_uart5_hwmod,
+ &am33xx_uart6_hwmod,
+ /* timer class */
+ &am33xx_timer0_hwmod,
+ &am33xx_timer1_hwmod,
+ &am33xx_timer2_hwmod,
+ &am33xx_timer3_hwmod,
+ &am33xx_timer4_hwmod,
+ &am33xx_timer5_hwmod,
+ &am33xx_timer6_hwmod,
+ &am33xx_timer7_hwmod,
+ /* wkup_m3 class */
+ &am33xx_wkup_m3_hwmod,
+ /* wd_timer class */
+ &am33xx_wd_timer1_hwmod,
+ /* usbss hwmod */
+ &am33xx_usbss_hwmod,
+ /* cpgmac0 class */
+ &am33xx_cpgmac0_hwmod,
+ &am33xx_wdt0_hwmod, /* Secure WDT */
+ /* tptc class */
+ &am33xx_tptc0_hwmod,
+ &am33xx_tptc1_hwmod,
+ &am33xx_tptc2_hwmod,
+ /* tpcc class */
+ &am33xx_tpcc_hwmod,
+ /* LCDC class */
+ &am33xx_lcdc_hwmod,
+ NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+ return omap_hwmod_register(am33xx_hwmods);
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8b372ed..db2ef2c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -612,5 +612,6 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
#endif
--
1.7.0.4
--
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