On Thu, 2011-11-03 at 10:35 +0100, Koen Kooi wrote: > Op 25 okt. 2011, om 09:37 heeft Tomi Valkeinen het volgende geschreven: > > > Hi, > > > > On Mon, 2011-10-24 at 13:55 -0400, Peter Barada wrote: > >> > >> In the above case (and my case where I'm looking for a 9Mhz pixel > >> clock), fck_div is calculated at higher than 16 - and the video > >> output > >> is wrong (i.e. no pixel clock and hsync runs at 32x the requested > >> rate). > > > > DM37x TRM says: > > > > "DSS1_ALWON_FCLK: Issued from DPLL4. Its frequency can be a division by > > 1 to 16 of the frequency of the DPLL4 synthesized clock." > > > > I take it that DM37x is detected as cpu_is_3630()? > > > > The DSS driver currently handles only OMAPs, so for other SoCs the > > driver may contain lots of bugs like this. > > dm3730 is just a different marketing name for omap3630, it should not have any functional changes. According to the TRM and experiments by Peter, it does. Tomi
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