Hi, On Mon, 2011-10-24 at 13:55 -0400, Peter Barada wrote: > > In the above case (and my case where I'm looking for a 9Mhz pixel > clock), fck_div is calculated at higher than 16 - and the video > output > is wrong (i.e. no pixel clock and hsync runs at 32x the requested > rate). DM37x TRM says: "DSS1_ALWON_FCLK: Issued from DPLL4. Its frequency can be a division by 1 to 16 of the frequency of the DPLL4 synthesized clock." I take it that DM37x is detected as cpu_is_3630()? The DSS driver currently handles only OMAPs, so for other SoCs the driver may contain lots of bugs like this. Tomi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
