RE: [PATCH 0/2] omap_wdt: fix interface clock handling

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> -----Original Message-----
> From: ext Cousson, Benoit [mailto:b-cousson@xxxxxx]
> 
> In theory, you should not have to disable the interface clock at all.
> Assuming that the smartidle is working properly, the iclk should be gated
> during clock domain transition automagically.
> The only thing that can prevent that is potentially a wrong setting in the
> clockactivity bits? It should be 0x2, meaning fclk is active but iclk can be gated.

Just trying that out now :)

- Kalle

> 
> Regards,
> Benoit
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