ext Robert Wörle wrote:
> Hi List
>
> I am running into issues , when using ttyS1 on a heavy loaded
> application. It trys to send and recieve around 60bytes every 100ms with
> 57600baud. There is a PIC Microcontroller attached on the otherside
> which immidiatly returns the data when requested.
>
> After some hours , the kernel starts to flood with the above messages
> and the system gets into an unusable state.
>
> i am running 2.6.35.9 ( released from isee.com ) on their Igep Module (
> arch igep0030).
>
> What would you guys do ? Anything i can provide you to help here ? Its
> really a major issue for us and showstopping an important release.
>
> Thanks in advance for any help or suggestion
>
Not sure if this is the same cause, but here's some code that fixed a similar issue:
Serial: 8250.c: Clear FIFOs before enabling them
There's a short time when FIFO's are disabled and interrupts enabled
between startup and set_termios.
If rx FIFO is not cleared before enabled, and there are lots of serial I/O,
an interrupt indicating FIFO data error can occur.
(LSR register bit 7 set, no other error bits set).
The current interrupt handle is unable to clear this interrupt and will continue looping with a
flood of "too much work" messages.
This is seen on an omap board with ST16654 type uart if a key is kept pressed in serial console while
booting.
Signed-off-by: Mathias Nyman <mathias.nyman@xxxxxxxxx>
---
drivers/serial/8250.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 5ed1b82..d3add25 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -2403,6 +2403,8 @@ serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
if (fcr & UART_FCR_ENABLE_FIFO) {
/* emulated UARTs (Lucent Venus 167x) need two steps */
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
+ serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
+ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
}
serial_outp(up, UART_FCR, fcr); /* set fcr */
}
--
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