On Wed, 19 Jan 2011, Vishwanath Sripathy wrote: > If some parts of the chip are busy, then how can Core domain enter off > state? The necessary condition for Core to enter low power state is that > all the clock domains (including DSS, CAM, IVA, USB, PER etc) should have > idled. Doesn't it mean that all the modules have idled and asserted > idleack when Core is entering off state? Some modules can operate autonomously from the rest of the system. For example, McBSP or DSS. They can indicate that they are idle or in standby while their FIFO(s) are draining or filling. At this point, the CORE clockdomains can potentially go inactive, even though the module is still operating autonomously. Once the module's FIFO watermark has been reached, the modules can deassert their SIdleAck or deassert MStandby and wake the system back up. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
