Hi, I was going through the DSS2 code which sets up the FCLK coming from PRCM and the DISPC divivors to get the required pixel clock. The function dss_calc_clock_div() does a brute force search across all possible values of: a) DPLL divisor whose output goes to DSS, b) DISPC_DIVISOR.LCD, c) DISPC_DIVISOR.pcd The combination which gives a clock frequency closest to the required pixel clock is chosen. Hence, it seems that the resultant DISPC_FCLK clock frequency doesn't take into account the extra margin needed for downscaling: Req dispc_fclk >= pck * hscale_ratio * vscale_ration * K Do you thing putting a further constraint (like DISPC_FCLK needs to be greater than a given value) should be a part of the calculations to ensure successful scaling? Regards, Archit-- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
