Re: [PATCHv4 12/14] OMAP: dmtimer: switch-over to platform device driver

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<<snip>>

> -/*
> - * Reads timer registers in posted and non-posted mode. The posted mode bit
> - * is encoded in reg. Note that in posted mode write pending bit must be
> - * checked. Otherwise a read of a non completed write will produce an error.
> +/**
> + * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
> + * @timer:      timer pointer over which read operation to perform
> + * @reg:        lowest byte holds the register offset
> + *
> + * The posted mode bit is encoded in reg. Note that in posted mode write
> + * pending bit must be checked. Otherwise a read of a non completed write
> + * will produce an error.
>  */
>  static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
>  {
> +       struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> +
> +       if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> +               reg += pdata->func_offst;
> +
>        if (timer->posted)
> -               while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
> -                               & (reg >> WPSHIFT))
> +               while (readl(timer->io_base +
> +                       ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
> +                               & 0xff)) & (reg >> WPSHIFT))

You may add a timeout in this.

>                        cpu_relax();
>        return readl(timer->io_base + (reg & 0xff));
>  }
>
> -/*
> - * Writes timer registers in posted and non-posted mode. The posted mode bit
> - * is encoded in reg. Note that in posted mode the write pending bit must be
> - * checked. Otherwise a write on a register which has a pending write will be
> - * lost.
> +/**
> + * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
> + * @timer:      timer pointer over which write operation is to perform
> + * @reg:        lowest byte holds the register offset
> + * @value:      data to write into the register
> + *
> + * The posted mode bit is encoded in reg. Note that in posted mode the write
> + * pending bit must be checked. Otherwise a write on a register which has a
> + * pending write will be lost.
>  */
>  static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
>                                                u32 value)
>  {
> +       struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> +
> +       if (reg >= OMAP_TIMER_WAKEUP_EN_REG)
> +               reg += pdata->func_offst;
> +
>        if (timer->posted)
> -               while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
> -                               & (reg >> WPSHIFT))
> +               while (readl(timer->io_base +
> +                       ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
> +                               & 0xff)) & (reg >> WPSHIFT))

Ditto.

>                        cpu_relax();
>        writel(value, timer->io_base + (reg & 0xff));
>  }


<<snip>>
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