Add low level read/write routines to access dmtimer interrupt
registers. These routines would be used later when we support
OMAP 4 new IP revision. When that happens the present read/write
routines would be used to access dmtimer functional registers
only.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@xxxxxx>
Signed-off-by: Partha Basak <p-basak2@xxxxxx>
Reviewed-by: Cousson, Benoit <b-cousson@xxxxxx>
---
arch/arm/plat-omap/dmtimer.c | 51 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 958acb8..0479ab0 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -307,6 +307,57 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
writel(value, timer->io_base + (reg & 0xff));
}
+/**
+ * omap_dm_timer_read_intr_reg - read timer interrupt registers in posted
+ * and non-posted mode
+ * @timer: timer pointer over which read operation to perform
+ * @reg: lowest byte holds the register offset
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode write
+ * pending bit must be checked. Otherwise a read of a non completed write
+ * will produce an error.
+ */
+static inline
+u32 omap_dm_timer_read_intr_reg(struct omap_dm_timer *timer, u32 reg)
+{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
+ reg += pdata->intr_offst;
+ if (timer->posted)
+ while (readl(timer->io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
+ & 0xff)) & (reg >> WPSHIFT))
+ cpu_relax();
+ return readl(timer->io_base + (reg & 0xff));
+}
+
+/**
+ * omap_dm_timer_write_intr_reg - write timer interrupt registers in posted
+ * and non-posted mode
+ * @timer: timer pointer over which write operation is to perform
+ * @reg: lowest byte holds the register offset
+ * @value: data to write into the register
+ *
+ * The posted mode bit is encoded in reg. Note that in posted mode the write
+ * pending bit must be checked. Otherwise a write on a register which has a
+ * pending write will be lost.
+ */
+static inline
+void omap_dm_timer_write_intr_reg(struct omap_dm_timer *timer, u32 reg,
+ u32 value)
+{
+ struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+
+ reg += pdata->intr_offst;
+ if (timer->posted)
+ while (readl(timer->io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG + pdata->func_offst)
+ & 0xff)) & (reg >> WPSHIFT))
+ cpu_relax();
+ writel(value, timer->io_base + (reg & 0xff));
+}
+
+
static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
{
int c;
--
1.6.0.4
--
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