On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren <tony@xxxxxxxxxxx> wrote: > * Nishanth Menon <nm@xxxxxx> [101118 08:46]: >> >> But after wfi in wait_sdrc_ok as part of the code executing in SRAM >> today omap34xx_cpu_suspend -> we are waiting for DPLL3 lock prior to >> accessing DDR -> how do we execute that logic in SDRAM? > I too am a bit concerned how this will all keep working. For light > testing it may be running OK if it happens to run from cache.. As Vishwa pointed out, when going out of OFF mode the SRAM and the caches are lost. That means the low power mode _has to_ rely on SDRAM at wake-up. About the DPLL lock: 1) wait_sdrc_ok is only called when back from the non-OFF modes, 2) I checked that when running wait_sdrc_ok the CORE is already out of idle and the DPLL is already locked. Note: l-o code has no support for the voltages OFF and the external clocks OFF. What to conclude from 1) and 2)? In my test setup ot looks like wait_sdrc_ok is of no use, but I agree this a premature conclusion. > Also, moving the code out of SRAM will limit the options for what we > may need to do with DDR or L3. What are the options? All the executable code runs from DDR anyway. > Retention is something to consider, are there issues with that? No issue so far. See the points 1) and 2) here above. > > Regards, > > Tony > Jean -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
