Hi Benoît, Thara, On Wed, 29 Sep 2010, Kevin Hilman wrote: > Also, I'm still seeing this on boot: > > omap_hwmod: sr1_fck: missing clockdomain for sr1_fck. > omap_hwmod: sr2_fck: missing clockdomain for sr2_fck. > > We need a final solution for this problem as a prerequisite for this > series as well. I guess we need to figure out the appropriate clockdomains for sr1_fck and sr2_fck. Probably the strictly correct thing to do, vis-a-vis the hardware, is to place them into their own SmartReflex clockdomain/powerdomain. But the PRCM doesn't export separate control registers for those, and as I understand it, that clockdomain/powerdomain follows the CORE clockdomains/powerdomain. Another option would be to place them into the WKUP clockdomain. The source of these functional clocks in SR_ALWON_FCLK which in turn is generated by the PRM from SYS_CLK. But that won't increment the CORE clockdomains' use-counter when the SR functional clocks are running, which seems desirable if the SmartReflex clockdomain/powerdomain really does follow CORE. So it seems to me that the best thing to do might be to place these clocks into the CORE_L4 clockdomain. But perhaps you might have a different view? regards, - Paul
