<snip>..
> > > This is with the omap2plus_defconfig and after editing cmdline to have console set
> > > to ttyO2.
> > >
> > > Would be nice to have those fixed before we merge it.
> >
> > Rajendra, can you look into this on OMAP2? This is happening for Tony
> > on both n8x0 and 2430sdp.
>
> Sure, I'll have a look.
Kevin,
I saw 3 issues with the patch which adds OMAP2 hwmods which I never seem to have
caught with the boottest on 2430 that I tried before I posted the patches.
These were causing the hwmod enable at init to fail and subsequent idle would throw
WARN's
Looking back at my bootlog on 2430, I did see the "cannot be enable" errors during
hwmod init, but the WARN's never came and I seem to have overlooked these
errors.
The only reason I can think of why the WARN's were not thrown was if for some
reason (usecounting) the pm_runtime_put_sync's from the i2c driver were not
translating into a omap_device/hmwod disable/idle call.
Partial 2430 bootlog from pm-core branch..
----
<6>Clocking rate (Crystal/DPLL/MPU): 13.0/660/330 MHz
Clocking rate (Crystal/DPLL/MPU): 13.0/660/330 MHz
<4>omap_hwmod: i2c1: cannot clk_get main_clk i2c1_fck
omap_hwmod: i2c1: cannot clk_get main_clk i2c1_fck
<4>omap_hwmod: i2c2: cannot clk_get main_clk i2c2_fck
omap_hwmod: i2c2: cannot clk_get main_clk i2c2_fck
<4>omap_hwmod: i2c1: cannot be enabled (3)
omap_hwmod: i2c1: cannot be enabled (3)
<4>omap_hwmod: i2c2: cannot be enabled (3)
omap_hwmod: i2c2: cannot be enabled (3)
<6>GPMC revision 3.0
GPMC revision 3.0
<6>IRQ: Found an INTC at 0xfa0fe000 (revision 3.0) with 96 interrupts
IRQ: Found an INTC at 0xfa0fe000 (revision 3.0) with 96 interrupts
<6>Total of 96 interrupts on 1 active controller
Total of 96 interrupts on 1 active controller
<6>OMAP GPIO hardware version 2.4
OMAP GPIO hardware version 2.4
<6>OMAP clockevent source: GPTIMER1 at 32000 Hz
OMAP clockevent source: GPTIMER1 at 32000 Hz
Console: colour dummy device 80x30
Console: colour dummy device 80x30
<6>Calibrating delay loop... Calibrating delay loop... <c>320.37 BogoMIPS (lpj=1253376)
320.37 BogoMIPS (lpj=1253376)
<6>pid_max: default: 32768 minimum: 301
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
Mount-cache hash table entries: 512
<6>CPU: Testing write buffer coherency: CPU: Testing write buffer coherency: ok
ok
<6>regulator: core version 0.5
regulator: core version 0.5
<6>NET: Registered protocol family 16
NET: Registered protocol family 16
<7>mux: Setting signal i2c2_scl.i2c2_scl 0x0000 -> 0x0100
mux: Setting signal i2c2_scl.i2c2_scl 0x0000 -> 0x0100
<7>mux: Setting signal i2c2_sda.i2c2_sda 0x0000 -> 0x0100
mux: Setting signal i2c2_sda.i2c2_sda 0x0000 -> 0x0100
<3>look up for i2c2 successful
look up for i2c2 successful
<7>mux: Setting signal usb0hs_data1.usb0_dat 0x0004 -> 0x0004
mux: Setting signal usb0hs_data1.usb0_dat 0x0004 -> 0x0004
<7>mux: Setting signal usb0hs_data0.usb0_txen 0x0004 -> 0x0004
mux: Setting signal usb0hs_data0.usb0_txen 0x0004 -> 0x0004
<7>mux: Setting signal usb0hs_data2.usb0_se0 0x0004 -> 0x0004
mux: Setting signal usb0hs_data2.usb0_se0 0x0004 -> 0x0004
USB: hmc 0USB: hmc 0, usb0 3 wires, usb0 3 wires, Mini-AB on usb0, Mini-AB on usb0
<7>mux: Setting signal usb0hs_stp.usb0hs_stp 0x0018 -> 0x0018
mux: Setting signal usb0hs_stp.usb0hs_stp 0x0018 -> 0x0018
<7>mux: Setting signal gpio_149.gpio149 0x0018 -> 0x0103
mux: Setting signal gpio_149.gpio149 0x0018 -> 0x0103
<6>OMAP DMA hardware revision 4.0
OMAP DMA hardware revision 4.0
bio: create slab <bio-0> at 0
bio: create slab <bio-0> at 0
<4>omap_device: i2c_omap.1: new worst case activate latency 0: 2563476
omap_device: i2c_omap.1: new worst case activate latency 0: 2563476
<6>i2c_omap i2c_omap.1: bus 1 rev3.7 at 100 kHz
i2c_omap i2c_omap.1: bus 1 rev3.7 at 100 kHz
<6>i2c_omap i2c_omap.2: bus 2 rev3.7 at 2600 kHz
i2c_omap i2c_omap.2: bus 2 rev3.7 at 2600 kHz
----
These are the fixes that make it boot on 2430sdp. Should I repost the original patch with these fixes?
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 5986e2b..9a106c0 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -126,12 +126,12 @@
#define OMAP24XX_ST_HDQ_MASK (1 << 23)
#define OMAP2420_ST_I2C2_SHIFT 20
#define OMAP2420_ST_I2C2_MASK (1 << 20)
-#define OMAP2430_ST_I2CHS1_SHIFT 20
-#define OMAP2430_ST_I2CHS1_MASK (1 << 20)
+#define OMAP2430_ST_I2CHS1_SHIFT 19
+#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
#define OMAP2420_ST_I2C1_SHIFT 19
#define OMAP2420_ST_I2C1_MASK (1 << 19)
-#define OMAP2430_ST_I2CHS2_SHIFT 19
-#define OMAP2430_ST_I2CHS2_MASK (1 << 19)
+#define OMAP2430_ST_I2CHS2_SHIFT 20
+#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
#define OMAP24XX_ST_MCBSP2_SHIFT 16
#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
#define OMAP24XX_ST_MCBSP1_SHIFT 15
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 8bf46c1..ca4edd3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -504,6 +504,7 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
.main_clk = "i2c1_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP2420_EN_I2C1_SHIFT,
.idlest_reg_id = 1,
@@ -541,6 +542,7 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
.main_clk = "i2c2_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP2420_EN_I2C2_SHIFT,
.idlest_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 92f4ec0..9498847 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -502,7 +502,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
.sdma_reqs = i2c1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
- .main_clk = "i2c1_fck",
+ .main_clk = "i2chs1_fck",
.prcm = {
.omap2 = {
/*
@@ -513,6 +513,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
* additonal flags when clk handling is moved
* to hwmod framework.
*/
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
.idlest_reg_id = 1,
@@ -551,9 +552,10 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
.sdma_reqs = i2c2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
- .main_clk = "i2c2_fck",
+ .main_clk = "i2chs2_fck",
.prcm = {
.omap2 = {
+ .module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
.idlest_reg_id = 1,
>
> >
> > >> Note this also depends on a handful of patches from my pm-backports
> > >> branch, most of which you have picked into omap-testing, except for the
> > >> one I just posted to linux-arm-kernel:
> > >>
> > >> ARM: add cpu_idle_wait() to support CPUidle on SMP systems.
> > >>
> > >> This one is required now that the default config enables SMP.
> > >
> > > I'll apply that into omap-testing branch.
> >
> > Thanks,
> >
> > Kevin
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