Add data for OMAP4430 generated from HW pinout & register database.
Signed-off-by: Benoit Cousson <b-cousson@xxxxxx>
Cc: Tony Lindgren <tony@xxxxxxxxxxx>
Cc: Paul Walmsley <paul@xxxxxxxxx>
Cc: Kevin Hilman <khilman@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/mach-omap2/Kconfig | 3 +
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/mux.c | 2 +-
arch/arm/mach-omap2/mux.h | 13 +
arch/arm/mach-omap2/mux44xx.c | 944 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/mux44xx.h | 278 ++++++++++++
6 files changed, 1240 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/mux44xx.c
create mode 100644 arch/arm/mach-omap2/mux44xx.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..6aede64 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -84,6 +84,9 @@ config OMAP_PACKAGE_CUS
config OMAP_PACKAGE_CBP
bool
+config OMAP_PACKAGE_CBL
+ bool
+
comment "OMAP Board Type"
depends on ARCH_OMAP2PLUS
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 88d3a1e..ca34bf2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -41,6 +41,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
+obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 8285cb8..813f034 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -776,7 +776,7 @@ int __init omap_mux_init(struct mux_partition *partitions, u32 partitions_cnt,
mux_partitions_cnt = partitions_cnt;
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx() || cpu_is_omap44xx())
omap_mux_flags = MUXABLE_GPIO_MODE3;
omap_mux_init_package(superset, package_subset, package_balls);
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index da67501..0445123 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,6 +10,7 @@
#include "mux2420.h"
#include "mux2430.h"
#include "mux34xx.h"
+#include "mux44xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
@@ -37,6 +38,9 @@
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
+/* 44xx specific mux bit defines */
+#define OMAP_WAKEUP_EVENT (1 << 15)
+
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
@@ -58,6 +62,8 @@
/* Flags for omap_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
+#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */
+#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
@@ -202,6 +208,13 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
+ * omap4_mux_init() - initialize mux system with board specific set
+ * @board_mux: Board specific mux table
+ * @flags: OMAP package type used for the board
+ */
+int omap4_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(struct mux_partition *partitions, u32 partitions_cnt,
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
new file mode 100644
index 0000000..839a905
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -0,0 +1,944 @@
+\
+/*
+ * OMAP44xx ES2.0 pin mux definition
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@xxxxxx)
+ *
+ * - Based on mux34xx.c done by Tony Lindgren <tony@xxxxxxxxxxx>
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@xxxxxxxxxxxxxxx mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP4_MUXENTRY(M0, i, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .id = (i), \
+ .gpio = (g), \
+ .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
+}
+
+#else
+
+#define _OMAP4_MUXENTRY(M0, i, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .id = (i), \
+ .gpio = (g), \
+}
+
+#endif
+
+#define _OMAP4_BALLENTRY(M0, i, bb, bt) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .id = (i), \
+ .balls = { bb, bt }, \
+}
+
+/*
+ * Superset of all mux modes for omap4
+ */
+static struct omap_mux __initdata omap4_muxmodes[] = {
+ _OMAP4_MUXENTRY(SYS_NRESWARM, PAD_WKUP_ID, 0, "sys_nreswarm", NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(UART3_RX_IRRX, PAD_CORE_ID, 143, "uart3_rx_irrx",
+ "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, PAD_CORE_ID, 170,
+ "usbb2_hsic_strobe", NULL, NULL, "gpio_170", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT4, PAD_CORE_ID, 188, "sys_boot4", NULL, NULL,
+ "gpio_188", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_TX_IRTX, PAD_CORE_ID, 144, "uart3_tx_irtx",
+ "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT0, PAD_CORE_ID, 147, "sdmmc5_dat0",
+ "mcspi2_somi", "usbc1_icusb_rcv", "gpio_147", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT1, PAD_CORE_ID, 148, "sdmmc5_dat1", NULL,
+ "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT2, PAD_CORE_ID, 149, "sdmmc5_dat2",
+ "mcspi2_cs1", NULL, "gpio_149", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_DAT3, PAD_CORE_ID, 150, "sdmmc5_dat3",
+ "mcspi2_cs0", NULL, "gpio_150", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, PAD_CORE_ID, 157,
+ "usbb2_ulpitll_clk", "usbb2_ulpiphy_clk",
+ "sdmmc4_cmd", "gpio_157", "hsi2_cawake", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_IO, PAD_WKUP_ID, 0, "sim_io", NULL, NULL,
+ "gpio_wk0", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX2, PAD_CORE_ID, 0, "unipro_rx2", "kpd_row4",
+ NULL, "gpi_2", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT5, PAD_CORE_ID, 189, "sys_boot5", NULL, NULL,
+ "gpio_189", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX0, PAD_CORE_ID, 0, "unipro_rx0", "kpd_row0",
+ NULL, "gpi_175", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RX1, PAD_CORE_ID, 0, "unipro_rx1", "kpd_row2",
+ NULL, "gpi_177", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS2, PAD_CORE_ID, 139, "mcspi1_cs2",
+ "uart1_cts", "slimbus2_clock", "gpio_139", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS3, PAD_CORE_ID, 140, "mcspi1_cs3",
+ "uart1_rts", "slimbus2_data", "gpio_140", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS0, PAD_CORE_ID, 137, "mcspi1_cs0", NULL,
+ NULL, "gpio_137", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_CS1, PAD_CORE_ID, 138, "mcspi1_cs1",
+ "uart1_rx", NULL, "gpio_138", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CS0, PAD_CORE_ID, 154, "mcspi4_cs0",
+ "sdmmc4_dat3", NULL, "gpio_154", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NADV_ALE, PAD_CORE_ID, 56, "gpmc_nadv_ale",
+ "dsi1_te1", NULL, "gpio_56", "sys_ndmareq3", NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(MCSPI4_SIMO, PAD_CORE_ID, 152, "mcspi4_simo",
+ "sdmmc4_cmd", NULL, "gpio_152", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_RTS_SD, PAD_CORE_ID, 142, "uart3_rts_sd", NULL,
+ NULL, "gpio_142", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT2, PAD_CORE_ID, 186, "sys_boot2", NULL, NULL,
+ "gpio_186", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_TDI, PAD_WKUP_ID, 0, "jtag_tdi", NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TDO, PAD_WKUP_ID, 0, "jtag_tdo", NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, PAD_CORE_ID, 162,
+ "usbb2_ulpitll_dat1", "usbb2_ulpiphy_dat1",
+ "sdmmc4_dat3", "gpio_162", "hsi2_acdata",
+ "dispc2_data19", NULL, "reserved"),
+ _OMAP4_MUXENTRY(GPMC_A18, PAD_CORE_ID, 42, "gpmc_a18", "kpd_row6",
+ "c2c_datain2", "gpio_42", "venc_656_data2", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A19, PAD_CORE_ID, 43, "gpmc_a19", "kpd_row7",
+ "c2c_datain3", "gpio_43", "venc_656_data3", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A16, PAD_CORE_ID, 40, "gpmc_a16", "kpd_row4",
+ "c2c_datain0", "gpio_40", "venc_656_data0", NULL,
+ NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A17, PAD_CORE_ID, 41, "gpmc_a17", "kpd_row5",
+ "c2c_datain1", "gpio_41", "venc_656_data1", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_HSIC_DATA, PAD_CORE_ID, 169, "usbb2_hsic_data",
+ NULL, NULL, "gpio_169", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_PWR_REQ, PAD_WKUP_ID, 0, "sys_pwr_req", NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, PAD_CORE_ID, 85,
+ "usbb1_ulpitll_stp", "hsi1_cadata", "mcbsp4_clkr",
+ "gpio_85", "usbb1_ulpiphy_stp", "usbb1_mm_rxdp",
+ "hw_dbg21", "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, PAD_WKUP_ID, 29,
+ "sys_pwron_reset_out", NULL, NULL, "gpio_wk29", NULL,
+ NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SDMMC1_CLK, PAD_CORE_ID, 100, "sdmmc1_clk", NULL,
+ "dpm_emu19", "gpio_100", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, PAD_CORE_ID, 87,
+ "usbb1_ulpitll_nxt", "hsi1_acready", "mcbsp4_fsx",
+ "gpio_87", "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm",
+ "hw_dbg23", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, PAD_CORE_ID, 95,
+ "usbb1_ulpitll_dat7", "dmtimer11_pwm_evt",
+ "abe_mcbsp3_fsx", "gpio_95", "usbb1_ulpiphy_dat7",
+ "abe_dmic_clk3", "hw_dbg31", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, PAD_CORE_ID, 168,
+ "usbb2_ulpitll_dat7", "usbb2_ulpiphy_dat7",
+ "sdmmc3_clk", "gpio_168", "mcspi3_clk",
+ "dispc2_data11", NULL, "reserved"),
+ _OMAP4_MUXENTRY(MCSPI1_CLK, PAD_CORE_ID, 134, "mcspi1_clk", NULL,
+ NULL, "gpio_134", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, PAD_CORE_ID, 166,
+ "usbb2_ulpitll_dat5", "usbb2_ulpiphy_dat5",
+ "sdmmc3_dat3", "gpio_166", "mcspi3_cs0",
+ "dispc2_data13", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, PAD_CORE_ID, 165,
+ "usbb2_ulpitll_dat4", "usbb2_ulpiphy_dat4",
+ "sdmmc3_dat0", "gpio_165", "mcspi3_somi",
+ "dispc2_data14", NULL, "reserved"),
+ _OMAP4_MUXENTRY(UNIPRO_RY1, PAD_CORE_ID, 0, "unipro_ry1", "kpd_row3",
+ NULL, "gpi_178", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY0, PAD_CORE_ID, 0, "unipro_ry0", "kpd_row1",
+ NULL, "gpi_176", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, PAD_CORE_ID, 113, "abe_mcbsp2_fsx",
+ "mcspi2_cs0", "abe_mcasp_afsx", "gpio_113",
+ "usbb2_mm_txen", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NBE1, PAD_CORE_ID, 60, "gpmc_nbe1", NULL,
+ "c2c_dataout5", "gpio_60", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_AD15, PAD_CORE_ID, 39, "gpmc_ad15", "kpd_col3",
+ "c2c_data8", "gpio_39", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD14, PAD_CORE_ID, 38, "gpmc_ad14", "kpd_col2",
+ "c2c_data9", "gpio_38", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD11, PAD_CORE_ID, 35, "gpmc_ad11", "kpd_row3",
+ "c2c_data12", "gpio_35", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD10, PAD_CORE_ID, 34, "gpmc_ad10", "kpd_row2",
+ "c2c_data13", "gpio_34", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD13, PAD_CORE_ID, 37, "gpmc_ad13", "kpd_col1",
+ "c2c_data10", "gpio_37", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD12, PAD_CORE_ID, 36, "gpmc_ad12", "kpd_col0",
+ "c2c_data11", "gpio_36", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(HDQ_SIO, PAD_CORE_ID, 127, "hdq_sio", "i2c3_sccb",
+ "i2c2_sccb", "gpio_127", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_TMS_TMSC, PAD_WKUP_ID, 0, "jtag_tms_tmsc", NULL,
+ NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_RX, PAD_CORE_ID, 155, "uart4_rx", "sdmmc4_dat2",
+ NULL, "gpio_155", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, PAD_CORE_ID, 91,
+ "usbb1_ulpitll_dat3", "hsi1_caready", NULL, "gpio_91",
+ "usbb1_ulpiphy_dat3", "usbb1_mm_txen", "hw_dbg27",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(I2C1_SDA, PAD_CORE_ID, 0, "i2c1_sda", NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, PAD_CORE_ID, 114, "abe_mcbsp1_clkx",
+ "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_AD9, PAD_CORE_ID, 33, "gpmc_ad9", "kpd_row1",
+ "c2c_data14", "gpio_33", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD8, PAD_CORE_ID, 32, "gpmc_ad8", "kpd_row0",
+ "c2c_data15", "gpio_32", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD5, PAD_CORE_ID, 0, "gpmc_ad5", "sdmmc2_dat5",
+ "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK4_OUT, PAD_WKUP_ID, 8, "fref_clk4_out", NULL,
+ NULL, "gpio_wk8", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD7, PAD_CORE_ID, 0, "gpmc_ad7", "sdmmc2_dat7",
+ "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD1, PAD_CORE_ID, 0, "gpmc_ad1", "sdmmc2_dat1",
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD0, PAD_CORE_ID, 0, "gpmc_ad0", "sdmmc2_dat0",
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD3, PAD_CORE_ID, 0, "gpmc_ad3", "sdmmc2_dat3",
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD2, PAD_CORE_ID, 0, "gpmc_ad2", "sdmmc2_dat2",
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_CE, PAD_CORE_ID, 0, "usba0_otg_ce", NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(JTAG_TCK, PAD_WKUP_ID, 0, "jtag_tck", NULL, NULL,
+ NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, PAD_CORE_ID, 88,
+ "usbb1_ulpitll_dat0", "hsi1_acwake", "mcbsp4_clkx",
+ "gpio_88", "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv",
+ "hw_dbg24", "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX1, PAD_CORE_ID, 0, "csi22_dx1", NULL, NULL,
+ "gpi_79", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DX0, PAD_CORE_ID, 0, "csi22_dx0", NULL, NULL,
+ "gpi_77", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SCL, PAD_CORE_ID, 130, "i2c3_scl", NULL, NULL,
+ "gpio_130", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SCL, PAD_CORE_ID, 132, "i2c4_scl", NULL, NULL,
+ "gpio_132", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C3_SDA, PAD_CORE_ID, 131, "i2c3_sda", NULL, NULL,
+ "gpio_131", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI1_SIMO, PAD_CORE_ID, 136, "mcspi1_simo", NULL,
+ NULL, "gpio_136", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_XTAL_IN, PAD_WKUP_ID, 0, "fref_xtal_in", NULL,
+ NULL, NULL, "c2c_wakereqin", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SDMMC1_DAT0, PAD_CORE_ID, 102, "sdmmc1_dat0", NULL,
+ "dpm_emu18", "gpio_102", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT1, PAD_CORE_ID, 103, "sdmmc1_dat1", NULL,
+ "dpm_emu17", "gpio_103", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT2, PAD_CORE_ID, 104, "sdmmc1_dat2", NULL,
+ "dpm_emu16", "gpio_104", "jtag_tms_tmsc", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK3_REQ, PAD_WKUP_ID, 30, "fref_clk3_req",
+ "fref_clk1_req", "sys_drm_msecure", "gpio_wk30",
+ "c2c_wakereqin", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT4, PAD_CORE_ID, 106, "sdmmc1_dat4", NULL,
+ NULL, "gpio_106", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT5, PAD_CORE_ID, 107, "sdmmc1_dat5", NULL,
+ NULL, "gpio_107", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT6, PAD_CORE_ID, 108, "sdmmc1_dat6", NULL,
+ NULL, "gpio_108", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT7, PAD_CORE_ID, 109, "sdmmc1_dat7", NULL,
+ NULL, "gpio_109", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_SHUTTER, PAD_CORE_ID, 81, "cam_shutter", NULL,
+ NULL, "gpio_81", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RX, PAD_CORE_ID, 125, "uart2_rx", "sdmmc3_dat0",
+ NULL, "gpio_125", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, PAD_CORE_ID, 163,
+ "usbb2_ulpitll_dat2", "usbb2_ulpiphy_dat2",
+ "sdmmc3_dat2", "gpio_163", "hsi2_acflag",
+ "dispc2_data18", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, PAD_CORE_ID, 89,
+ "usbb1_ulpitll_dat1", "hsi1_acdata", "mcbsp4_dx",
+ "gpio_89", "usbb1_ulpiphy_dat1", "usbb1_mm_txse0",
+ "hw_dbg25", "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK3_OUT, PAD_WKUP_ID, 31, "fref_clk3_out",
+ "fref_clk2_req", "sys_secure_indicator", "gpio_wk31",
+ "c2c_wakereqout", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK2_OUT, PAD_CORE_ID, 182, "fref_clk2_out",
+ NULL, NULL, "gpio_182", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_CTS, PAD_CORE_ID, 123, "uart2_cts",
+ "sdmmc3_clk", NULL, "gpio_123", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_PWRCTRL, PAD_WKUP_ID, 4, "sim_pwrctrl", NULL,
+ NULL, "gpio_wk4", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY3, PAD_CORE_ID, 0, "csi21_dy3", NULL, NULL,
+ "gpi_74", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY2, PAD_CORE_ID, 0, "csi21_dy2", NULL, NULL,
+ "gpi_72", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY1, PAD_CORE_ID, 0, "csi21_dy1", NULL, NULL,
+ "gpi_70", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY0, PAD_CORE_ID, 0, "csi21_dy0", NULL, NULL,
+ "gpi_68", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DY4, PAD_CORE_ID, 0, "csi21_dy4", NULL, NULL,
+ "gpi_76", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY0, PAD_CORE_ID, 0, "csi22_dy0", NULL, NULL,
+ "gpi_78", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI22_DY1, PAD_CORE_ID, 0, "csi22_dy1", NULL, NULL,
+ "gpi_80", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C4_SDA, PAD_CORE_ID, 133, "i2c4_sda", NULL, NULL,
+ "gpio_133", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_AD6, PAD_CORE_ID, 0, "gpmc_ad6", "sdmmc2_dat6",
+ "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NWE, PAD_CORE_ID, 0, "gpmc_nwe", "sdmmc2_cmd",
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(DPM_EMU15, PAD_CORE_ID, 26, "dpm_emu15",
+ "sys_secure_indicator", NULL, "gpio_26", "rfbi_data4",
+ "dispc2_data4", "hw_dbg15", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU14, PAD_CORE_ID, 25, "dpm_emu14",
+ "sys_drm_msecure", "uart1_rx", "gpio_25",
+ "rfbi_data5", "dispc2_data5", "hw_dbg14", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU17, PAD_CORE_ID, 28, "dpm_emu17",
+ "dmtimer9_pwm_evt", "dsi1_te1", "gpio_28",
+ "rfbi_data2", "dispc2_data2", "hw_dbg17", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU16, PAD_CORE_ID, 27, "dpm_emu16",
+ "dmtimer8_pwm_evt", "dsi1_te0", "gpio_27",
+ "rfbi_data3", "dispc2_data3", "hw_dbg16", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU11, PAD_CORE_ID, 22, "dpm_emu11",
+ "usba0_ulpiphy_dat5", NULL, "gpio_22", "rfbi_data8",
+ "dispc2_data8", "hw_dbg11", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU10, PAD_CORE_ID, 21, "dpm_emu10",
+ "usba0_ulpiphy_dat4", NULL, "gpio_21", "rfbi_a0",
+ "dispc2_de", "hw_dbg10", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU13, PAD_CORE_ID, 24, "dpm_emu13",
+ "usba0_ulpiphy_dat7", NULL, "gpio_24", "rfbi_data6",
+ "dispc2_data6", "hw_dbg13", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU12, PAD_CORE_ID, 23, "dpm_emu12",
+ "usba0_ulpiphy_dat6", NULL, "gpio_23", "rfbi_data7",
+ "dispc2_data7", "hw_dbg12", "reserved"),
+ _OMAP4_MUXENTRY(ABE_CLKS, PAD_CORE_ID, 118, "abe_clks", NULL, NULL,
+ "gpio_118", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DR, PAD_CORE_ID, 115, "abe_mcbsp1_dr",
+ "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU19, PAD_CORE_ID, 191, "dpm_emu19",
+ "dmtimer11_pwm_evt", "dsi2_te1", "gpio_191",
+ "rfbi_data0", "dispc2_data0", "hw_dbg19", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU18, PAD_CORE_ID, 190, "dpm_emu18",
+ "dmtimer10_pwm_evt", "dsi2_te0", "gpio_190",
+ "rfbi_data1", "dispc2_data1", "hw_dbg18", "reserved"),
+ _OMAP4_MUXENTRY(GPMC_NWP, PAD_CORE_ID, 54, "gpmc_nwp", "dsi1_te0",
+ NULL, "gpio_54", "sys_ndmareq1", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK0_OUT, PAD_WKUP_ID, 6, "fref_clk0_out",
+ "fref_clk1_req", "sys_drm_msecure", "gpio_wk6", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NRESPWRON, PAD_WKUP_ID, 0, "sys_nrespwron", NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(CAM_GLOBALRESET, PAD_CORE_ID, 83, "cam_globalreset",
+ NULL, NULL, "gpio_83", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C1_SCL, PAD_CORE_ID, 0, "i2c1_scl", NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(CSI21_DX4, PAD_CORE_ID, 0, "csi21_dx4", NULL, NULL,
+ "gpi_75", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_NTRST, PAD_WKUP_ID, 0, "jtag_ntrst", NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(CSI21_DX0, PAD_CORE_ID, 0, "csi21_dx0", NULL, NULL,
+ "gpi_67", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX1, PAD_CORE_ID, 0, "csi21_dx1", NULL, NULL,
+ "gpi_69", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX2, PAD_CORE_ID, 0, "csi21_dx2", NULL, NULL,
+ "gpi_71", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(CSI21_DX3, PAD_CORE_ID, 0, "csi21_dx3", NULL, NULL,
+ "gpi_73", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_CMD, PAD_CORE_ID, 101, "sdmmc1_cmd", NULL,
+ "uart1_rx", "gpio_101", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK_IOREQ, PAD_WKUP_ID, 0, "fref_clk_ioreq",
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SR_SCL, PAD_WKUP_ID, 0, "sr_scl", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DX, PAD_CORE_ID, 112, "abe_mcbsp2_dx",
+ "mcspi2_simo", "abe_mcasp_amute", "gpio_112",
+ "usbb2_mm_rxrcv", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_DR, PAD_CORE_ID, 111, "abe_mcbsp2_dr",
+ "mcspi2_somi", "abe_mcasp_axr", "gpio_111",
+ "usbb2_mm_rxdp", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, PAD_CORE_ID, 0, "abe_pdm_dl_data",
+ "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_NIRQ2, PAD_CORE_ID, 183, "sys_nirq2", NULL, NULL,
+ "gpio_183", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CLK, PAD_CORE_ID, 145, "sdmmc5_clk",
+ "mcspi2_clk", "usbc1_icusb_dp", "gpio_145", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_SOMI, PAD_CORE_ID, 153, "mcspi4_somi",
+ "sdmmc4_dat0", NULL, "gpio_153", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, PAD_CORE_ID, 160,
+ "usbb2_ulpitll_nxt", "usbb2_ulpiphy_nxt",
+ "sdmmc4_dat1", "gpio_160", "hsi2_acready",
+ "dispc2_data21", NULL, "reserved"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN1, PAD_CORE_ID, 120, "abe_dmic_din1",
+ NULL, NULL, "gpio_120", "usbb2_mm_txdat", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(CAM_STROBE, PAD_CORE_ID, 82, "cam_strobe", NULL, NULL,
+ "gpio_82", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN3, PAD_CORE_ID, 122, "abe_dmic_din3",
+ "slimbus2_data", "abe_dmic_clk2", "gpio_122", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN2, PAD_CORE_ID, 121, "abe_dmic_din2",
+ "slimbus2_clock", NULL, "gpio_121", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_CEC, PAD_CORE_ID, 64, "hdmi_cec", NULL, NULL,
+ "gpio_64", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, PAD_CORE_ID, 110, "abe_mcbsp2_clkx",
+ "mcspi2_clk", "abe_mcasp_ahclkx", "gpio_110",
+ "usbb2_mm_rxdm", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, PAD_CORE_ID, 0, "abe_pdm_lb_clk",
+ "abe_mcbsp3_fsx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_RTS, PAD_CORE_ID, 124, "uart2_rts",
+ "sdmmc3_cmd", NULL, "gpio_124", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU9, PAD_CORE_ID, 20, "dpm_emu9",
+ "usba0_ulpiphy_dat3", "uart3_cts_rctx", "gpio_20",
+ "rfbi_we", "dispc2_vsync", "hw_dbg9", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU8, PAD_CORE_ID, 19, "dpm_emu8",
+ "usba0_ulpiphy_dat2", "uart3_rts_sd", "gpio_19",
+ "rfbi_re", "dispc2_pclk", "hw_dbg8", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU5, PAD_CORE_ID, 16, "dpm_emu5",
+ "usba0_ulpiphy_nxt", NULL, "gpio_16",
+ "rfbi_te_vsync0", "dispc2_data16", "hw_dbg5",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU4, PAD_CORE_ID, 15, "dpm_emu4",
+ "usba0_ulpiphy_dir", NULL, "gpio_15", NULL,
+ "dispc2_data9", "hw_dbg4", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU7, PAD_CORE_ID, 18, "dpm_emu7",
+ "usba0_ulpiphy_dat1", "uart3_rx_irrx", "gpio_18",
+ "rfbi_cs0", "dispc2_hsync", "hw_dbg7", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU6, PAD_CORE_ID, 17, "dpm_emu6",
+ "usba0_ulpiphy_dat0", "uart3_tx_irtx", "gpio_17",
+ "rfbi_hsync0", "dispc2_data17", "hw_dbg6",
+ "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU1, PAD_CORE_ID, 12, "dpm_emu1", NULL, NULL,
+ "gpio_12", NULL, NULL, "hw_dbg1", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU0, PAD_CORE_ID, 11, "dpm_emu0", NULL, NULL,
+ "gpio_11", NULL, NULL, "hw_dbg0", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU3, PAD_CORE_ID, 14, "dpm_emu3",
+ "usba0_ulpiphy_stp", NULL, "gpio_14", NULL,
+ "dispc2_data10", "hw_dbg3", "reserved"),
+ _OMAP4_MUXENTRY(DPM_EMU2, PAD_CORE_ID, 13, "dpm_emu2",
+ "usba0_ulpiphy_clk", NULL, "gpio_13", NULL,
+ "dispc2_fid", "hw_dbg2", "reserved"),
+ _OMAP4_MUXENTRY(SYS_NIRQ1, PAD_CORE_ID, 0, "sys_nirq1", NULL, NULL,
+ NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_CLK1, PAD_CORE_ID, 119, "abe_dmic_clk1",
+ NULL, NULL, "gpio_119", "usbb2_mm_txse0", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UART2_TX, PAD_CORE_ID, 126, "uart2_tx", "sdmmc3_dat1",
+ NULL, "gpio_126", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT7, PAD_WKUP_ID, 10, "sys_boot7", "dpm_emu19",
+ NULL, "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT6, PAD_WKUP_ID, 9, "sys_boot6", "dpm_emu18",
+ NULL, "gpio_wk9", "c2c_wakereqout", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_CLK, PAD_CORE_ID, 55, "gpmc_clk", NULL, NULL,
+ "gpio_55", "sys_ndmareq2", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SYS_BOOT1, PAD_CORE_ID, 185, "sys_boot1", NULL, NULL,
+ "gpio_185", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT0, PAD_CORE_ID, 184, "sys_boot0", NULL, NULL,
+ "gpio_184", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_SLICER_IN, PAD_WKUP_ID, 0, "fref_slicer_in",
+ NULL, NULL, "gpi_wk5", "c2c_wakereqin", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, PAD_CORE_ID, 86,
+ "usbb1_ulpitll_dir", "hsi1_caflag", "mcbsp4_fsr",
+ "gpio_86", "usbb1_ulpiphy_dir", NULL, "hw_dbg22",
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_RY2, PAD_CORE_ID, 0, "unipro_ry2", "kpd_row5",
+ NULL, "gpi_3", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_HPD, PAD_CORE_ID, 63, "hdmi_hpd", NULL, NULL,
+ "gpio_63", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SYS_BOOT3, PAD_CORE_ID, 187, "sys_boot3", NULL, NULL,
+ "gpio_187", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_CD, PAD_WKUP_ID, 3, "sim_cd", NULL, NULL,
+ "gpio_wk3", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX0, PAD_CORE_ID, 171, "unipro_tx0",
+ "kpd_col0", NULL, "gpio_171", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX1, PAD_CORE_ID, 173, "unipro_tx1",
+ "kpd_col2", NULL, "gpio_173", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SR_SDA, PAD_WKUP_ID, 0, "sr_sda", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(SDMMC5_CMD, PAD_CORE_ID, 146, "sdmmc5_cmd",
+ "mcspi2_simo", "usbc1_icusb_dm", "gpio_146", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SDA, PAD_CORE_ID, 66, "hdmi_ddc_sda", NULL,
+ NULL, "gpio_66", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(I2C2_SDA, PAD_CORE_ID, 129, "i2c2_sda", "uart1_tx",
+ NULL, "gpio_129", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, PAD_CORE_ID, 167,
+ "usbb2_ulpitll_dat6", "usbb2_ulpiphy_dat6",
+ "sdmmc3_cmd", "gpio_167", "mcspi3_simo",
+ "dispc2_data12", NULL, "reserved"),
+ _OMAP4_MUXENTRY(SYS_32K, PAD_WKUP_ID, 0, "sys_32k", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DM, PAD_CORE_ID, 99, "usbc1_icusb_dm",
+ NULL, NULL, "gpio_99", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_DM, PAD_CORE_ID, 180, "usba0_otg_dm",
+ "uart3_tx_irtx", "uart2_tx", "gpio_180", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBC1_ICUSB_DP, PAD_CORE_ID, 98, "usbc1_icusb_dp",
+ NULL, NULL, "gpio_98", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART3_CTS_RCTX, PAD_CORE_ID, 141, "uart3_cts_rctx",
+ "uart1_tx", NULL, "gpio_141", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, PAD_CORE_ID, 97,
+ "usbb1_hsic_strobe", NULL, NULL, "gpio_97", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(JTAG_RTCK, PAD_WKUP_ID, 0, "jtag_rtck", NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(MCSPI1_SOMI, PAD_CORE_ID, 135, "mcspi1_somi", NULL,
+ NULL, "gpio_135", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(HDMI_DDC_SCL, PAD_CORE_ID, 65, "hdmi_ddc_scl", NULL,
+ NULL, "gpio_65", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_DX, PAD_CORE_ID, 116, "abe_mcbsp1_dx",
+ "sdmmc3_dat2", "abe_mcasp_aclkx", "gpio_116", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA14, PAD_CORE_ID, 103, "c2c_data14",
+ "dsi2_te0", "c2c_dataout0", "gpio_103",
+ "sys_ndmareq3", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA15, PAD_CORE_ID, 104, "c2c_data15",
+ "dsi2_te1", "c2c_dataout1", "gpio_104", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA11, PAD_CORE_ID, 100, "c2c_data11",
+ "usbc1_icusb_txen", "c2c_dataout3", "gpio_100",
+ "sys_ndmareq0", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA12, PAD_CORE_ID, 101, "c2c_data12",
+ "dsi1_te0", "c2c_clkin0", "gpio_101", "sys_ndmareq1",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(C2C_DATA13, PAD_CORE_ID, 102, "c2c_data13",
+ "dsi1_te1", "c2c_clkin1", "gpio_102", "sys_ndmareq2",
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS1, PAD_CORE_ID, 51, "gpmc_ncs1", NULL,
+ "c2c_dataout6", "gpio_51", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS0, PAD_CORE_ID, 50, "gpmc_ncs0", NULL, NULL,
+ "gpio_50", "sys_ndmareq0", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NCS3, PAD_CORE_ID, 53, "gpmc_ncs3", "gpmc_dir",
+ "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS2, PAD_CORE_ID, 52, "gpmc_ncs2", NULL,
+ "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, PAD_CORE_ID, 94,
+ "usbb1_ulpitll_dat6", "dmtimer10_pwm_evt",
+ "abe_mcbsp3_clkx", "gpio_94", "usbb1_ulpiphy_dat6",
+ "abe_dmic_din3", "hw_dbg30", "safe_mode"),
+ _OMAP4_MUXENTRY(MCSPI4_CLK, PAD_CORE_ID, 151, "mcspi4_clk",
+ "sdmmc4_clk", NULL, "gpio_151", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, PAD_CORE_ID, 92,
+ "usbb1_ulpitll_dat4", "dmtimer8_pwm_evt",
+ "abe_mcbsp3_dr", "gpio_92", "usbb1_ulpiphy_dat4",
+ NULL, "hw_dbg28", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, PAD_CORE_ID, 93,
+ "usbb1_ulpitll_dat5", "dmtimer9_pwm_evt",
+ "abe_mcbsp3_dx", "gpio_93", "usbb1_ulpiphy_dat5",
+ NULL, "hw_dbg29", "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, PAD_CORE_ID, 90,
+ "usbb1_ulpitll_dat2", "hsi1_acflag", "mcbsp4_dr",
+ "gpio_90", "usbb1_ulpiphy_dat2", "usbb1_mm_txdat",
+ "hw_dbg26", "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY2, PAD_CORE_ID, 1, "unipro_ty2", "kpd_col5",
+ NULL, "gpio_1", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY1, PAD_CORE_ID, 174, "unipro_ty1",
+ "kpd_col3", NULL, "gpio_174", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TY0, PAD_CORE_ID, 172, "unipro_ty0",
+ "kpd_col1", NULL, "gpio_172", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, PAD_CORE_ID, 161,
+ "usbb2_ulpitll_dat0", "usbb2_ulpiphy_dat0",
+ "sdmmc4_dat2", "gpio_161", "hsi2_acwake",
+ "dispc2_data20", NULL, "reserved"),
+ _OMAP4_MUXENTRY(I2C2_SCL, PAD_CORE_ID, 128, "i2c2_scl", "uart1_rx",
+ NULL, "gpio_128", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, PAD_CORE_ID, 0, "abe_pdm_ul_data",
+ "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(FREF_CLK1_OUT, PAD_CORE_ID, 181, "fref_clk1_out",
+ NULL, NULL, "gpio_181", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC1_DAT3, PAD_CORE_ID, 105, "sdmmc1_dat3", NULL,
+ "dpm_emu15", "gpio_105", "jtag_tck", NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(SIM_RESET, PAD_WKUP_ID, 2, "sim_reset", NULL, NULL,
+ "gpio_wk2", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_HSIC_DATA, PAD_CORE_ID, 96, "usbb1_hsic_data",
+ NULL, NULL, "gpio_96", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_AD4, PAD_CORE_ID, 0, "gpmc_ad4", "sdmmc2_dat4",
+ "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(FREF_CLK4_REQ, PAD_WKUP_ID, 7, "fref_clk4_req",
+ "fref_clk5_out", NULL, "gpio_wk7", NULL, NULL, NULL,
+ NULL),
+ _OMAP4_MUXENTRY(SIM_CLK, PAD_WKUP_ID, 1, "sim_clk", NULL, NULL,
+ "gpio_wk1", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT1, PAD_CORE_ID, 62, "gpmc_wait1", NULL,
+ "c2c_dataout2", "gpio_62", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, PAD_CORE_ID, 158,
+ "usbb2_ulpitll_stp", "usbb2_ulpiphy_stp",
+ "sdmmc4_clk", "gpio_158", "hsi2_cadata",
+ "dispc2_data23", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, PAD_CORE_ID, 164,
+ "usbb2_ulpitll_dat3", "usbb2_ulpiphy_dat3",
+ "sdmmc3_dat1", "gpio_164", "hsi2_caready",
+ "dispc2_data15", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, PAD_CORE_ID, 159,
+ "usbb2_ulpitll_dir", "usbb2_ulpiphy_dir",
+ "sdmmc4_dat0", "gpio_159", "hsi2_caflag",
+ "dispc2_data22", NULL, "reserved"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, PAD_CORE_ID, 84,
+ "usbb1_ulpitll_clk", "hsi1_cawake", NULL, "gpio_84",
+ "usbb1_ulpiphy_clk", NULL, "hw_dbg20", "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT0, PAD_CORE_ID, 61, "gpmc_wait0", "dsi2_te1",
+ NULL, "gpio_61", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_DP, PAD_CORE_ID, 179, "usba0_otg_dp",
+ "uart3_rx_irrx", "uart2_rx", "gpio_179", NULL, NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NOE, PAD_CORE_ID, 0, "gpmc_noe", "sdmmc2_clk",
+ NULL, NULL, NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(ABE_PDM_FRAME, PAD_CORE_ID, 0, "abe_pdm_frame",
+ "abe_mcbsp3_clkx", NULL, NULL, NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, PAD_CORE_ID, 117, "abe_mcbsp1_fsx",
+ "sdmmc3_dat3", "abe_mcasp_amutein", "gpio_117", NULL,
+ NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_TX, PAD_CORE_ID, 156, "uart4_tx", "sdmmc4_dat1",
+ NULL, "gpio_156", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NBE0_CLE, PAD_CORE_ID, 59, "gpmc_nbe0_cle",
+ "dsi2_te0", NULL, "gpio_59", NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A23, PAD_CORE_ID, 47, "gpmc_a23", "kpd_col7",
+ "c2c_datain7", "gpio_47", "venc_656_data7", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A22, PAD_CORE_ID, 46, "gpmc_a22", "kpd_col6",
+ "c2c_datain6", "gpio_46", "venc_656_data6", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A21, PAD_CORE_ID, 45, "gpmc_a21", "kpd_col5",
+ "c2c_datain5", "gpio_45", "venc_656_data5", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A20, PAD_CORE_ID, 44, "gpmc_a20", "kpd_col4",
+ "c2c_datain4", "gpio_44", "venc_656_data4", NULL,
+ NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UNIPRO_TX2, PAD_CORE_ID, 0, "unipro_tx2", "kpd_col4",
+ NULL, "gpio_0", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A25, PAD_CORE_ID, 49, "gpmc_a25", NULL,
+ "c2c_clkout1", "gpio_49", NULL, NULL, NULL,
+ "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A24, PAD_CORE_ID, 48, "gpmc_a24", NULL,
+ "c2c_clkout0", "gpio_48", NULL, NULL, NULL,
+ "safe_mode"),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL package
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ * 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
+ && defined (CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_cbl_ball[] = {
+ _OMAP4_BALLENTRY(SYS_NRESWARM, PAD_WKUP_ID, "af7", NULL),
+ _OMAP4_BALLENTRY(UART3_RX_IRRX, PAD_CORE_ID, "g27", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, PAD_CORE_ID, "ae13", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT4, PAD_CORE_ID, "d28", NULL),
+ _OMAP4_BALLENTRY(UART3_TX_IRTX, PAD_CORE_ID, "g28", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT0, PAD_CORE_ID, "ae4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT1, PAD_CORE_ID, "af4", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT2, PAD_CORE_ID, "ag3", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_DAT3, PAD_CORE_ID, "af3", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, PAD_CORE_ID, "ag12", NULL),
+ _OMAP4_BALLENTRY(SIM_IO, PAD_WKUP_ID, "h4", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX2, PAD_CORE_ID, "l27", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT5, PAD_CORE_ID, "d27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX0, PAD_CORE_ID, "j26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RX1, PAD_CORE_ID, "k26", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS2, PAD_CORE_ID, "ag23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS3, PAD_CORE_ID, "ah23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS0, PAD_CORE_ID, "ae23", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CS1, PAD_CORE_ID, "af23", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CS0, PAD_CORE_ID, "ae20", NULL),
+ _OMAP4_BALLENTRY(GPMC_NADV_ALE, PAD_CORE_ID, "d25", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SIMO, PAD_CORE_ID, "af20", NULL),
+ _OMAP4_BALLENTRY(UART3_RTS_SD, PAD_CORE_ID, "f28", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT2, PAD_CORE_ID, "e26", NULL),
+ _OMAP4_BALLENTRY(JTAG_TDI, PAD_WKUP_ID, "ae1", NULL),
+ _OMAP4_BALLENTRY(JTAG_TDO, PAD_WKUP_ID, "ae2", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, PAD_CORE_ID, "af11", NULL),
+ _OMAP4_BALLENTRY(GPMC_A18, PAD_CORE_ID, "b18", NULL),
+ _OMAP4_BALLENTRY(GPMC_A19, PAD_CORE_ID, "a19", NULL),
+ _OMAP4_BALLENTRY(GPMC_A16, PAD_CORE_ID, "b17", NULL),
+ _OMAP4_BALLENTRY(GPMC_A17, PAD_CORE_ID, "a18", NULL),
+ _OMAP4_BALLENTRY(USBB2_HSIC_DATA, PAD_CORE_ID, "af13", NULL),
+ _OMAP4_BALLENTRY(SYS_PWR_REQ, PAD_WKUP_ID, "ah7", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, PAD_CORE_ID, "ag19", NULL),
+ _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, PAD_WKUP_ID, "ag6", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CLK, PAD_CORE_ID, "d2", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, PAD_CORE_ID, "ae19", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, PAD_CORE_ID, "ag16", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, PAD_CORE_ID, "ae9", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_CLK, PAD_CORE_ID, "af22", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, PAD_CORE_ID, "af10", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, PAD_CORE_ID, "ae10", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY1, PAD_CORE_ID, "k25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY0, PAD_CORE_ID, "j25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, PAD_CORE_ID, "ac28", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE1, PAD_CORE_ID, "d22", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD15, PAD_CORE_ID, "d19", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD14, PAD_CORE_ID, "c19", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD11, PAD_CORE_ID, "d17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD10, PAD_CORE_ID, "c17", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD13, PAD_CORE_ID, "d18", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD12, PAD_CORE_ID, "c18", NULL),
+ _OMAP4_BALLENTRY(HDQ_SIO, PAD_CORE_ID, "aa27", NULL),
+ _OMAP4_BALLENTRY(JTAG_TMS_TMSC, PAD_WKUP_ID, "ah1", NULL),
+ _OMAP4_BALLENTRY(UART4_RX, PAD_CORE_ID, "ag20", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, PAD_CORE_ID, "af17", NULL),
+ _OMAP4_BALLENTRY(I2C1_SDA, PAD_CORE_ID, "ae26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, PAD_CORE_ID, "ac26", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD9, PAD_CORE_ID, "d16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD8, PAD_CORE_ID, "c16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD5, PAD_CORE_ID, "d15", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK4_OUT, PAD_WKUP_ID, "ac3", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD7, PAD_CORE_ID, "b16", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD1, PAD_CORE_ID, "d12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD0, PAD_CORE_ID, "c12", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD3, PAD_CORE_ID, "d13", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD2, PAD_CORE_ID, "c13", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_CE, PAD_CORE_ID, "c3", NULL),
+ _OMAP4_BALLENTRY(JTAG_TCK, PAD_WKUP_ID, "ag1", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, PAD_CORE_ID, "af18", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX1, PAD_CORE_ID, "n26", NULL),
+ _OMAP4_BALLENTRY(CSI22_DX0, PAD_CORE_ID, "m26", NULL),
+ _OMAP4_BALLENTRY(I2C3_SCL, PAD_CORE_ID, "w27", NULL),
+ _OMAP4_BALLENTRY(I2C4_SCL, PAD_CORE_ID, "ag21", NULL),
+ _OMAP4_BALLENTRY(I2C3_SDA, PAD_CORE_ID, "y27", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SIMO, PAD_CORE_ID, "ag22", NULL),
+ _OMAP4_BALLENTRY(FREF_XTAL_IN, PAD_WKUP_ID, "ah6", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT0, PAD_CORE_ID, "e4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT1, PAD_CORE_ID, "e2", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT2, PAD_CORE_ID, "e1", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK3_REQ, PAD_WKUP_ID, "ad3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT4, PAD_CORE_ID, "f3", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT5, PAD_CORE_ID, "f1", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT6, PAD_CORE_ID, "g4", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT7, PAD_CORE_ID, "g3", NULL),
+ _OMAP4_BALLENTRY(CAM_SHUTTER, PAD_CORE_ID, "t27", NULL),
+ _OMAP4_BALLENTRY(UART2_RX, PAD_CORE_ID, "aa25", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, PAD_CORE_ID, "ag11", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, PAD_CORE_ID, "ag18", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK3_OUT, PAD_WKUP_ID, "ad4", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK2_OUT, PAD_CORE_ID, "y28", NULL),
+ _OMAP4_BALLENTRY(UART2_CTS, PAD_CORE_ID, "ab26", NULL),
+ _OMAP4_BALLENTRY(SIM_PWRCTRL, PAD_WKUP_ID, "k1", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY3, PAD_CORE_ID, "v25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY2, PAD_CORE_ID, "u25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY1, PAD_CORE_ID, "t25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY0, PAD_CORE_ID, "r25", NULL),
+ _OMAP4_BALLENTRY(CSI21_DY4, PAD_CORE_ID, "w25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY0, PAD_CORE_ID, "m25", NULL),
+ _OMAP4_BALLENTRY(CSI22_DY1, PAD_CORE_ID, "n25", NULL),
+ _OMAP4_BALLENTRY(I2C4_SDA, PAD_CORE_ID, "ah22", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD6, PAD_CORE_ID, "a16", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWE, PAD_CORE_ID, "b12", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU15, PAD_CORE_ID, "aa4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU14, PAD_CORE_ID, "aa3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU17, PAD_CORE_ID, "ab3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU16, PAD_CORE_ID, "ab2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU11, PAD_CORE_ID, "y4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU10, PAD_CORE_ID, "y3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU13, PAD_CORE_ID, "aa2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU12, PAD_CORE_ID, "aa1", NULL),
+ _OMAP4_BALLENTRY(ABE_CLKS, PAD_CORE_ID, "ah26", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DR, PAD_CORE_ID, "ac25", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU19, PAD_CORE_ID, "ac4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU18, PAD_CORE_ID, "ab4", NULL),
+ _OMAP4_BALLENTRY(GPMC_NWP, PAD_CORE_ID, "c25", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK0_OUT, PAD_WKUP_ID, "ad2", NULL),
+ _OMAP4_BALLENTRY(SYS_NRESPWRON, PAD_WKUP_ID, "ae7", NULL),
+ _OMAP4_BALLENTRY(CAM_GLOBALRESET, PAD_CORE_ID, "v27", NULL),
+ _OMAP4_BALLENTRY(I2C1_SCL, PAD_CORE_ID, "ae28", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX4, PAD_CORE_ID, "w26", NULL),
+ _OMAP4_BALLENTRY(JTAG_NTRST, PAD_WKUP_ID, "ah2", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX0, PAD_CORE_ID, "r26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX1, PAD_CORE_ID, "t26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX2, PAD_CORE_ID, "u26", NULL),
+ _OMAP4_BALLENTRY(CSI21_DX3, PAD_CORE_ID, "v26", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_CMD, PAD_CORE_ID, "e3", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK_IOREQ, PAD_WKUP_ID, "ad1", NULL),
+ _OMAP4_BALLENTRY(SR_SCL, PAD_WKUP_ID, "ag9", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DX, PAD_CORE_ID, "ad25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_DR, PAD_CORE_ID, "ad26", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, PAD_CORE_ID, "af25", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ2, PAD_CORE_ID, "af6", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CLK, PAD_CORE_ID, "ae5", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_SOMI, PAD_CORE_ID, "af21", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, PAD_CORE_ID, "ag13", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN1, PAD_CORE_ID, "af24", NULL),
+ _OMAP4_BALLENTRY(CAM_STROBE, PAD_CORE_ID, "u27", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN3, PAD_CORE_ID, "ah24", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_DIN2, PAD_CORE_ID, "ag24", NULL),
+ _OMAP4_BALLENTRY(HDMI_CEC, PAD_CORE_ID, "b10", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, PAD_CORE_ID, "ad27", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, PAD_CORE_ID, "af26", NULL),
+ _OMAP4_BALLENTRY(UART2_RTS, PAD_CORE_ID, "ab27", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU9, PAD_CORE_ID, "y2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU8, PAD_CORE_ID, "w4", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU5, PAD_CORE_ID, "w1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU4, PAD_CORE_ID, "v2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU7, PAD_CORE_ID, "w3", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU6, PAD_CORE_ID, "w2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU1, PAD_CORE_ID, "n2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU0, PAD_CORE_ID, "m2", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU3, PAD_CORE_ID, "v1", NULL),
+ _OMAP4_BALLENTRY(DPM_EMU2, PAD_CORE_ID, "p2", NULL),
+ _OMAP4_BALLENTRY(SYS_NIRQ1, PAD_CORE_ID, "ae6", NULL),
+ _OMAP4_BALLENTRY(ABE_DMIC_CLK1, PAD_CORE_ID, "ae24", NULL),
+ _OMAP4_BALLENTRY(UART2_TX, PAD_CORE_ID, "aa26", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT7, PAD_WKUP_ID, "ae8", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT6, PAD_WKUP_ID, "af8", NULL),
+ _OMAP4_BALLENTRY(GPMC_CLK, PAD_CORE_ID, "b22", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT1, PAD_CORE_ID, "e27", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT0, PAD_CORE_ID, "f26", NULL),
+ _OMAP4_BALLENTRY(FREF_SLICER_IN, PAD_WKUP_ID, "ag8", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, PAD_CORE_ID, "af19", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_RY2, PAD_CORE_ID, "k27", NULL),
+ _OMAP4_BALLENTRY(HDMI_HPD, PAD_CORE_ID, "b9", NULL),
+ _OMAP4_BALLENTRY(SYS_BOOT3, PAD_CORE_ID, "e25", NULL),
+ _OMAP4_BALLENTRY(SIM_CD, PAD_WKUP_ID, "j1", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX0, PAD_CORE_ID, "g26", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX1, PAD_CORE_ID, "h26", NULL),
+ _OMAP4_BALLENTRY(SR_SDA, PAD_WKUP_ID, "af9", NULL),
+ _OMAP4_BALLENTRY(SDMMC5_CMD, PAD_CORE_ID, "af5", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SDA, PAD_CORE_ID, "b8", NULL),
+ _OMAP4_BALLENTRY(I2C2_SDA, PAD_CORE_ID, "d26", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, PAD_CORE_ID, "ag10", NULL),
+ _OMAP4_BALLENTRY(SYS_32K, PAD_WKUP_ID, "ag7", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DM, PAD_CORE_ID, "h3", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DM, PAD_CORE_ID, "b4", NULL),
+ _OMAP4_BALLENTRY(USBC1_ICUSB_DP, PAD_CORE_ID, "h2", NULL),
+ _OMAP4_BALLENTRY(UART3_CTS_RCTX, PAD_CORE_ID, "f27", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, PAD_CORE_ID, "ae14", NULL),
+ _OMAP4_BALLENTRY(JTAG_RTCK, PAD_WKUP_ID, "ae3", NULL),
+ _OMAP4_BALLENTRY(MCSPI1_SOMI, PAD_CORE_ID, "ae22", NULL),
+ _OMAP4_BALLENTRY(HDMI_DDC_SCL, PAD_CORE_ID, "a8", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_DX, PAD_CORE_ID, "ab25", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA14, PAD_CORE_ID, "c24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA15, PAD_CORE_ID, "d24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA11, PAD_CORE_ID, "d23", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA12, PAD_CORE_ID, "a24", NULL),
+ _OMAP4_BALLENTRY(C2C_DATA13, PAD_CORE_ID, "b24", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS1, PAD_CORE_ID, "c21", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS0, PAD_CORE_ID, "b25", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS3, PAD_CORE_ID, "c22", NULL),
+ _OMAP4_BALLENTRY(GPMC_NCS2, PAD_CORE_ID, "d21", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, PAD_CORE_ID, "af16", NULL),
+ _OMAP4_BALLENTRY(MCSPI4_CLK, PAD_CORE_ID, "ae21", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, PAD_CORE_ID, "ah17", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, PAD_CORE_ID, "ae16", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, PAD_CORE_ID, "ae17", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY2, PAD_CORE_ID, "h27", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY1, PAD_CORE_ID, "h25", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TY0, PAD_CORE_ID, "g25", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, PAD_CORE_ID, "ae11", NULL),
+ _OMAP4_BALLENTRY(I2C2_SCL, PAD_CORE_ID, "c26", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, PAD_CORE_ID, "ag25", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK1_OUT, PAD_CORE_ID, "aa28", NULL),
+ _OMAP4_BALLENTRY(SDMMC1_DAT3, PAD_CORE_ID, "f4", NULL),
+ _OMAP4_BALLENTRY(SIM_RESET, PAD_WKUP_ID, "g2", NULL),
+ _OMAP4_BALLENTRY(USBB1_HSIC_DATA, PAD_CORE_ID, "af14", NULL),
+ _OMAP4_BALLENTRY(GPMC_AD4, PAD_CORE_ID, "c15", NULL),
+ _OMAP4_BALLENTRY(FREF_CLK4_REQ, PAD_WKUP_ID, "ac2", NULL),
+ _OMAP4_BALLENTRY(SIM_CLK, PAD_WKUP_ID, "j2", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT1, PAD_CORE_ID, "b23", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, PAD_CORE_ID, "af12", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, PAD_CORE_ID, "ah11", NULL),
+ _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, PAD_CORE_ID, "ae12", NULL),
+ _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, PAD_CORE_ID, "ae18", NULL),
+ _OMAP4_BALLENTRY(GPMC_WAIT0, PAD_CORE_ID, "b26", NULL),
+ _OMAP4_BALLENTRY(USBA0_OTG_DP, PAD_CORE_ID, "b5", NULL),
+ _OMAP4_BALLENTRY(GPMC_NOE, PAD_CORE_ID, "b11", NULL),
+ _OMAP4_BALLENTRY(ABE_PDM_FRAME, PAD_CORE_ID, "ae25", NULL),
+ _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, PAD_CORE_ID, "ac27", NULL),
+ _OMAP4_BALLENTRY(UART4_TX, PAD_CORE_ID, "ah19", NULL),
+ _OMAP4_BALLENTRY(GPMC_NBE0_CLE, PAD_CORE_ID, "c23", NULL),
+ _OMAP4_BALLENTRY(GPMC_A23, PAD_CORE_ID, "b21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A22, PAD_CORE_ID, "a21", NULL),
+ _OMAP4_BALLENTRY(GPMC_A21, PAD_CORE_ID, "b20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A20, PAD_CORE_ID, "b19", NULL),
+ _OMAP4_BALLENTRY(UNIPRO_TX2, PAD_CORE_ID, "j27", NULL),
+ _OMAP4_BALLENTRY(GPMC_A25, PAD_CORE_ID, "d20", NULL),
+ _OMAP4_BALLENTRY(GPMC_A24, PAD_CORE_ID, "c20", NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_cbl_ball NULL
+#endif
+
+static __initdata struct mux_partition omap4_mux_partitions[] = {
+ [PAD_CORE_ID] = {
+ .phys = OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
+ .size = OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
+ },
+ [PAD_WKUP_ID] = {
+ .phys = OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
+ .size = OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
+ },
+};
+
+int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+ struct omap_ball *package_balls;
+
+ switch (flags & OMAP_PACKAGE_MASK) {
+ case OMAP_PACKAGE_CBL:
+ package_balls = omap4_cbl_ball;
+ break;
+ default:
+ pr_err("mux: Unknown omap package, mux disabled\n");
+ return -EINVAL;
+ }
+
+ return omap_mux_init(omap4_mux_partitions,
+ ARRAY_SIZE(omap4_mux_partitions),
+ omap4_muxmodes, NULL, board_subset,
+ package_balls);
+}
+
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
new file mode 100644
index 0000000..217758a
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -0,0 +1,278 @@
+/*
+ * OMAP44xx MUX registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@xxxxxx)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@xxxxxxxxxxxxxxx mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+
+#define OMAP4_MUX(M0, i, mux_value) \
+{ \
+ .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
+ .id = (i), \
+ .value = (mux_value), \
+}
+
+/* ctrl_module_pad_core base address*/
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
+
+/* ctrl_module_pad_core registers offset*/
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
+#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
+#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
+#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
+#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
+#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
+#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
+#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
+#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
+#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
+#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
+#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
+#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
+#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
+#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
+#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
+#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
+#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
+
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
+ (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
+ - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
+
+/* ctrl_module_pad_wkup base address*/
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
+
+/* ctrl_module_pad_wkup registers offset*/
+#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
+#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
+#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
+#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
+#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
+#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
+#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
+#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
+#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
+#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
+#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
+#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
+
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
+ (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
+ - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
+
+#endif
--
1.6.0.4
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