> -----Original Message----- > From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap- > owner@xxxxxxxxxxxxxxx] On Behalf Of Woodruff, Richard > Sent: Thursday, September 16, 2010 11:36 AM > To: Paul Walmsley; Hunter, Jon > Cc: linux-omap; khilman@xxxxxxxxxxxxxxxxxxx; tony@xxxxxxxxxxx > Subject: RE: [PATCH] omap3: Prevent SDRC deadlock when L3 is changing > frequency > > > > From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap- > > owner@xxxxxxxxxxxxxxx] On Behalf Of Paul Walmsley > > Sent: Wednesday, September 15, 2010 2:15 PM > > > > This patch fixes this problem by ensuring the branch prediction logic > is > > > disabled while changing the L3 clock frequency. The branch prediction > logic > > > is disabled by clearing the Z-bit in the ARM AUX CTRL register. > > Small correction, Z bit is in CR register. AUX CTRL figures in with the > ASA feature. > > > Really nice changelog. I wish every patch had a description this good. > > Patch looks really good, too. Queued for 2.6.37. > > It is system specific if this change is required. It is probably safer to > have it than not. > > If the AUX CTRL register has the ASA bit/feature active to allow > speculative accesses to propagate past the L2 boundary the Z bit should be > cleared as in the patch. > > However, if ASA bit is not activated then Z bit clearing should not be > necessary as speculation will be squashed if there is no L2 hit (so no DDR > request will be generated). > > It is not recommended to enable ASA bit as it is known to cause some > issues on EMU/HS devices. It was also projected as loosing more than it > gained across some benchmarks. > > Early boot loaders used to set the ASA. It was removed long back. Some > kernels kept the value and opened up the lockup window. I don't recall > the linux-omap open kernel having the issue. Some vendor ones did over > time. > The code seems to be correct but just the description has typo. The code is using control register. I just corrected the description and white space issue. Here is updated patch. Paul, You can use this version if you like >From fd4250671a1ae8deb718ac3688ea8971df7524cf Mon Sep 17 00:00:00 2001 From: Jon Hunter <jon-hunter@xxxxxx> Date: Thu, 16 Sep 2010 12:03:23 +0530 Subject: [PATCH] omap3: Prevent SDRC deadlock when L3 is changing frequency When changing the L3 clock frequency, the CPU is executing from internal RAM and the SDRC clock is disabled. During this time accesses made to external DDR are stalled. If the ARM subsystem attempts to access the DDR while the SDRC clock is disabled this will stall the CPU until the access to the SDRC timeouts. A timeout on the SDRC should never occur. Once a timeout occurs all the following accesses will be aborted and the DDR is no longer accessible. Although the code being executed in the internal RAM does not directly access the DDR, it was found that the branch prediction logic in the CPU may cause the CPU to prefetch code from a DDR location while the SDRC clock is disabled. This was causing an SDRC timeout which resulted in a system hang. This patch fixes this problem by ensuring the branch prediction logic is disabled while changing the L3 clock frequency. The branch prediction logic is disabled by clearing the Z-bit in the ARM CTRL register. Disabling the branch prediction logic does not have any noticable impact on the execution time of this code section. The hardware observability signals were used to monitor the sdrc idle time with and without this patch when operating at different CPU frequencies (150MHz, 500MHz and 600MHz) and the total sdrc idle time when changing frequenct was in the range of 9-11us. This was measured on an omap3430 SDP running the omapzoom p-android-omap-2.6.29 branch. Signed-off-by: Jon Hunter <jon-hunter@xxxxxx> --- arch/arm/mach-omap2/sram34xx.S | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index de99ba2..3637274 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #80] str r4, omap_sdrc_mr_1_val skip_cs1_params: + mrc p15, 0, r8, c1, c0, 0 @ read ctrl register + bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction + mcr p15, 0, r10, c1, c0, 0 @ write ctrl register dsb @ flush buffered writes to interconnect - + isb @ prevent speculative exec past here cmp r3, #1 @ if increasing SDRC clk rate, bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state @@ -148,6 +151,7 @@ skip_cs1_params: beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now return_to_sdram: + mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return -- 1.6.0.4
Attachment:
0001-omap3-Prevent-SDRC-deadlock-when-L3-is-changing-fre.patch
Description: 0001-omap3-Prevent-SDRC-deadlock-when-L3-is-changing-fre.patch
