RE: [PATCH] omap3: Prevent SDRC deadlock when L3 is changing frequency

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> From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap-
> owner@xxxxxxxxxxxxxxx] On Behalf Of Paul Walmsley
> Sent: Wednesday, September 15, 2010 2:15 PM

> > This patch fixes this problem by ensuring the branch prediction logic is
> > disabled while changing the L3 clock frequency. The branch prediction logic
> > is disabled by clearing the Z-bit in the ARM AUX CTRL register.

Small correction, Z bit is in CR register. AUX CTRL figures in with the ASA feature.

> Really nice changelog.  I wish every patch had a description this good.
> Patch looks really good, too.  Queued for 2.6.37.

It is system specific if this change is required. It is probably safer to have it than not.

If the AUX CTRL register has the ASA bit/feature active to allow speculative accesses to propagate past the L2 boundary the Z bit should be cleared as in the patch.

However, if ASA bit is not activated then Z bit clearing should not be necessary as speculation will be squashed if there is no L2 hit (so no DDR request will be generated).

It is not recommended to enable ASA bit as it is known to cause some issues on EMU/HS devices. It was also projected as loosing more than it gained across some benchmarks.

Early boot loaders used to set the ASA.  It was removed long back.  Some kernels kept the value and opened up the lockup window.  I don't recall the linux-omap open kernel having the issue. Some vendor ones did over time.

Regards,
Richard W.

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