RE: [PATCH V4 0/2] OMAP3: Dynamic Calculation of SDRC stall latency during DVFS

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Pramod, Teerth,

On Thu, 1 Jul 2010, Paul Walmsley wrote:

> Pramod, Teerth,
> 
> On Mon, 7 Jun 2010, Gurav , Pramod wrote:
> 
> > Can you please push these patches if you don't you are OK with them?
> 
> As we discussed in Bangalore, these patches need some changes:
> 
> 1. The delay needs to be precisely characterized in terms of what the 
> hardware actually needs.  It should not be necessary to add any extra 
> timing slop, due to unknown sources, in the code.  Unknown sources of 
> delay can cause problems if, for example, a customer changes some board 
> characteristics (such as sys_clk frequency, or DPLL multipliers/dividers) 
> that the delay depends on.
> 
> Also, my understanding is that RX-51 shipped without unknown timing 
> factors in this code.  Please work with the hardware people to precisely 
> characterize the delay, assuming that it does not match what is documented 
> in the TRM.
> 
> 2. Please split out the individual components of the delay calculation to 
> the code that handles those clocks.  For example, HSDIVIDER change delay 
> should be calculated by code that handles the HSDIVIDER.  DPLL relock 
> delay should be calculated by code in the dpll*.c files.  etc.

Any updates on these patches?


- Paul
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