On Tue, Apr 13, 2010 at 3:37 PM, Vishwanath BS <vishwanath.bs@xxxxxx> wrote: > From: Teerth Reddy <teerth@xxxxxx> > > This patch has the workaround for errata 1.176. > In some cases, user is not able to access DDR memory after > warm-reset.This situation occurs while the warm-reset > happens during a read access to DDR memory. In that > particular conditions, DDR memory does not respond to a > corrupted read command due to the warm reset occurence but > SDRC is waiting for read completion.SDRC is not sensitive to > the warm reset, but the interconect is reset on the fly, > thus causing a misalignment between SDRC logic, interconect > logic and DDR memory state. > > Root cause description: A corrupted read transaction is > issued to a closed row: (address0, bank0) instead of the > expected read access, violating protocol. > > Failure signature: Once the failure occurs and system has > restarted, memory content is not accessible.SDRC registers > can be accessed successfully, until 1st access to memory > location is performed. After 1st access to memory is done, > SDRC is stuck. > > WORKAROUND > Steps to perform before a SW reset is trigged, if user needs > to generate a SW reset and keep DDR memory content: > 1. Enable self-refresh on idle request > 2. Put SDRC in idle > 3. Wait until SDRC goes to idle > 4. Generate SW reset > > Steps to perform after warm reset occurs: > If HW warm reset is the source, apply below steps before > any accesses to SDRAM: > 1. Reset SMS and SDRC > 2. Re-initialize SMS, SDRC and memory > > This would need the u-boot/x-loader workaround changes > as well for the reboot to work correctly. > > Signed-off-by: Teerth Reddy <teerth@xxxxxx> > Signed-off-by: Vishwanath BS <vishwanath.bs@xxxxxx> > --- <snip> > diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S > index de99ba2..1a1be4d > --- a/arch/arm/mach-omap2/sram34xx.S > +++ b/arch/arm/mach-omap2/sram34xx.S > @@ -33,6 +33,8 @@ > > #include "sdrc.h" > #include "cm.h" > +#include "prcm-common.h" > +#include "prm.h" > > .text > > @@ -68,6 +70,9 @@ > /* CM_CLKSEL1_PLL bit settings */ > #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b > > +/* PRM_RSTCTRL bit setting */ > +#define EN_DPLL3_RESET 0x4 > + > /* > * omap3_sram_configure_core_dpll - change DPLL3 M2 divider > * > @@ -313,3 +318,49 @@ core_m2_mask_val: > ENTRY(omap3_sram_configure_core_dpll_sz) > .word . - omap3_sram_configure_core_dpll > > + > +/* > +* omap3_sram_configure_core_dpll_warmreset > +* Enable SDRC self refresh on idle request, put SDRC in idle, > +* wait until SDRC goes to idle > +* Enable DPLL3 reset bit in RM_RSTCTRL > +*/ > + > +ENTRY(omap3_sram_configure_core_dpll_warmreset) don't you need to stack some registers here? r9, r11 and lr are callee-saved. > + > + bl sdram_in_selfrefresh1 > + ldr r11, omap3_reset_cntrl > + ldr r12, [r11] > + orr r12, r12, #EN_DPLL3_RESET @ Enable DPLL3 reset bit > + str r12, [r11] > + > +sdram_in_selfrefresh1: > + ldr r11, omap3_sdrc_power1 @ read the SDRC_POWER register > + ldr r12, [r11] @ read the contents of SDRC_POWER > + mov r9, r12 @ keep a copy of SDRC_POWER bits where is this used? > + orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle > + str r12, [r11] @ write back to SDRC_POWER register > + ldr r12, [r11] @ posted-write barrier for SDRC > + ldr r11, omap3_cm_iclken1_core1 @ read the CM_ICLKEN1_CORE reg > + ldr r12, [r11] > + bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC > + str r12, [r11] > +wait_sdrc_idle2: > + ldr r11, omap3_cm_idlest1_core1 > + ldr r12, [r11] > + and r12, r12, #ST_SDRC_MASK @ check for SDRC idle > + cmp r12, #ST_SDRC_MASK > + bne wait_sdrc_idle2 > + bx lr Are you positive this code actually works? To me it looks like it could deadlock. > + > +omap3_reset_cntrl: > + .word OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL) > +omap3_sdrc_power1: > + .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) > +omap3_cm_idlest1_core1: > + .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) > +omap3_cm_iclken1_core1: > + .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) > + > +ENTRY(omap3_sram_configure_core_dpll_warmreset_sz) > + .word . - omap3_sram_configure_core_dpll_warmreset <snip> -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
