DSP usage at VDD1 OPP1 and OPP2 with Smartreflex enabled and any MM UCs running DSP codec was earlier restricted as DSP crashed. The root cause is wrong DPLL1/DPLL2 Bypass clock at VDD1 OPP1 and OPP2. The solution is to make sure DPLL1/DPLL2 bypass clock is always less than maximum supported frequency for the specific OPP. Typically these settings are to be done in bootloaders. All the patches have been tested on OMAP3630 ZOOM3 platform. Comments adressed in V3: 1. Used clk_set_rate API instead of directly writing to registers 2. Split the patch into 2 patches. Vishwanath BS (4): OMAP3: Set MPU and IVA bypass Clock Divider OMAP3 PM: Set MPU and IVA bypass clock dividers in DVFS 2 files changed, 12 insertions(+), 0 deletions(-) arch/arm/mach-omap2/clock3xxx_data.c | 12 ++++++++++++ arch/arm/mach-omap2/resource34xx.c | 18 ++++++++++++++++-- -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
