> -----Original Message----- > From: Paul Walmsley [mailto:paul@xxxxxxxxx] > Sent: Tuesday, March 30, 2010 3:01 PM > To: Sripathy, Vishwanath > Cc: Kevin Hilman; linux-omap@xxxxxxxxxxxxxxx; Gulati, Shweta > Subject: RE: [PATCHV2] OMAP3 PM: Fix for DSP Crash at OPP 1 and 2 under > DVFS+SR operation > > On Mon, 29 Mar 2010, Sripathy, Vishwanath wrote: > > > > -----Original Message----- > > > From: Kevin Hilman [mailto:khilman@xxxxxxxxxxxxxxxxxxx] > > > > > > Please add this support by modifying/extending the existing clock/DPLL > > > management code instead of manually writing registers. > > > > > Min/max dividers in clock framework are for dpll lock frequency, where > > as in the patch, we configure dpll bypass frequency. Shall I add a new > > API in dpll.c to configure bypass clock dividers? > > That API is called clk_set_rate() and is already present as you can see by > grep'ping clock3xxx_data.c for OMAP3430_MPU_CLK_SRC_MASK (as one example). > Thanks, I will repost the patch. > > - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
