Kevin, > -----Original Message----- > From: Kevin Hilman [mailto:khilman@xxxxxxxxxxxxxxxxxxx] > Sent: Wednesday, March 17, 2010 11:32 PM > To: Sripathy, Vishwanath > Cc: linux-omap@xxxxxxxxxxxxxxx; Gulati, Shweta > Subject: Re: [PATCHV2] OMAP3 PM: Fix for DSP Crash at OPP 1 and 2 under > DVFS+SR operation > > Vishwanath BS <vishwanath.bs@xxxxxx> writes: > > > From: Shweta Gulati <shweta.gulati@xxxxxx> > > > > DSP usage at VDD1 OPP1 and OPP2 with Smartreflex enabled and any MM UCs > > running DSP codec was earlier restricted as DSP crashed. > > The root cause is wrong DPLL1/DPLL2 Bypass clock at VDD1 OPP1 and OPP2. > > The solution is to make sure DPLL1/DPLL2 bypass clock is always less than > > maximum supported frequency for the specific OPP > > > > Tested on 3630 ZOOM3. > > > > changes in V2 : Rebased to new OPP implementation > > > > Signed-off-by: Shweta Gulati <shweta.gulati@xxxxxx> > > Signed-off-by: Vishwanath BS <vishwanath.bs@xxxxxx> > > --- > > This should be broken up into two parts. One that applies to mainline > (or l-o master), and another that fixes SRF that can be applied to PM > branch. The first will be targted for mainline, but the SRF change > will be only in PM branch, as SRF is deprecated and will be replaced. ack > > That being said, the approach in this patch is not the right approach. > It appears to completely ignore the min/max dividers that are already > managed by the clock/DPLL code. > > Please add this support by modifying/extending the existing clock/DPLL > management code instead of manually writing registers. > Min/max dividers in clock framework are for dpll lock frequency, where as in the patch, we configure dpll bypass frequency. Shall I add a new API in dpll.c to configure bypass clock dividers? Vishwa > Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
