Hello Vishwanath,
some more comments:
On Thu, 7 Jan 2010, Vishwanath BS wrote:
> In 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This
> patch has changes to support this feature. 96MHz clock is generated by
> dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register.
> SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's
> functional clock. In summary changes done are
> 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630
> 2. Added a new clock node called omap_192m_alwon_ck
> 3. Made omap_96m_alwon_fck to derive it's clock from omap_192m_alwon_ck
>
> Cc: Paul Walmsley <paul@xxxxxxxxx>
>
> Signed-off-by: Vishwanath BS <Vishwanath.bs@xxxxxx>
> ---
> arch/arm/mach-omap2/clock34xx_data.c | 72 ++++++++++++++++++++++++++++-----
> arch/arm/mach-omap2/cm-regbits-34xx.h | 2 +
> arch/arm/mach-omap2/id.c | 3 +
> arch/arm/plat-omap/include/plat/cpu.h | 2 +
> 4 files changed, 68 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
> index 04c8e3c..bb9922f 100755
> --- a/arch/arm/mach-omap2/clock34xx_data.c
> +++ b/arch/arm/mach-omap2/clock34xx_data.c
> @@ -700,18 +700,24 @@ static struct clk dpll4_m2x2_ck = {
> * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
> * CM_96K_(F)CLK.
> */
> -static struct clk omap_96m_alwon_fck = {
> - .name = "omap_96m_alwon_fck",
> - .ops = &clkops_null,
> - .parent = &dpll4_m2x2_ck,
> - .recalc = &followparent_recalc,
> +
> +/* Adding 192MHz Clock node needed by SGX */
> +static struct clk omap_192m_alwon_ck = {
> + .name = "omap_192m_alwon_ck",
> + .ops = &clkops_null,
> + .parent = &dpll4_m2x2_ck,
> + .recalc = &followparent_recalc,
> };
>
> -static struct clk cm_96m_fck = {
> - .name = "cm_96m_fck",
> - .ops = &clkops_null,
> - .parent = &omap_96m_alwon_fck,
> - .recalc = &followparent_recalc,
> +static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
> + { .div = 1, .val = 1, .flags = RATE_IN_36XX },
> + { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
> + { .div = 0 }
> +};
> +
> +static const struct clksel omap_96m_alwon_fck_clksel[] = {
> + { .parent = &omap_192m_alwon_ck, .rates = omap_96m_alwon_fck_rates },
> + { .parent = NULL }
> };
>
> static const struct clksel_rate omap_96m_dpll_rates[] = {
> @@ -724,6 +730,31 @@ static const struct clksel_rate omap_96m_sys_rates[] = {
> { .div = 0 }
> };
>
> +static struct clk omap_96m_alwon_fck = {
> + .name = "omap_96m_alwon_fck",
> + .ops = &clkops_null,
> + .parent = &dpll4_m2x2_ck,
> + .recalc = &followparent_recalc,
> +};
> +
> +static struct clk omap_96m_alwon_fck_3630 = {
> + .name = "omap_96m_alwon_fck",
> + .parent = &omap_192m_alwon_ck,
> + .init = &omap2_init_clksel_parent,
> + .ops = &clkops_null,
> + .recalc = &omap2_clksel_recalc,
> + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
> + .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
> + .clksel = omap_96m_alwon_fck_clksel
> +};
Please follow the coding style of the rest of the file and tab-align the
above structure members consistently.
> +
> +static struct clk cm_96m_fck = {
> + .name = "cm_96m_fck",
> + .ops = &clkops_null,
> + .parent = &omap_96m_alwon_fck,
> + .recalc = &followparent_recalc,
> +};
> +
> static const struct clksel omap_96m_fck_clksel[] = {
> { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
> { .parent = &sys_ck, .rates = omap_96m_sys_rates },
> @@ -1306,12 +1337,24 @@ static struct clk gfx_cg2_ck = {
> /* SGX power domain - 3430ES2 only */
>
> static const struct clksel_rate sgx_core_rates[] = {
> + { .div = 2, .val = 5, .flags = RATE_IN_36XX },
> { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
> { .div = 4, .val = 1, .flags = RATE_IN_343X },
> { .div = 6, .val = 2, .flags = RATE_IN_343X },
> { .div = 0 },
> };
>
> +static const struct clksel_rate sgx_192m_rates[] = {
> + { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
> + { .div = 0 },
> +};
> +
> +static const struct clksel_rate sgx_corex2_rates[] = {
> + { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
> + { .div = 5, .val = 7, .flags = RATE_IN_36XX },
> + { .div = 0 },
> +};
> +
> static const struct clksel_rate sgx_96m_rates[] = {
> { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
> { .div = 0 },
> @@ -1320,7 +1363,9 @@ static const struct clksel_rate sgx_96m_rates[] = {
> static const struct clksel sgx_clksel[] = {
> { .parent = &core_ck, .rates = sgx_core_rates },
> { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
> - { .parent = NULL },
> + { .parent = &omap_192m_alwon_ck, .rates = sgx_192m_rates },
> + { .parent = &corex2_fck, .rates = sgx_corex2_rates },
> + { .parent = NULL }
> };
>
> static struct clk sgx_fck = {
> @@ -1334,6 +1379,8 @@ static struct clk sgx_fck = {
> .clksel = sgx_clksel,
> .clkdm_name = "sgx_clkdm",
> .recalc = &omap2_clksel_recalc,
> + .set_rate = &omap2_clksel_set_rate,
> + .round_rate = &omap2_clksel_round_rate
> };
>
> static struct clk sgx_ick = {
> @@ -3155,6 +3202,7 @@ static struct omap_clk omap3xxx_clks[] = {
> CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
> CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
> CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
> + CLK(NULL, "omap_192_alwon_fck", &omap_192m_alwon_ck, CK_36XX),
Please follow the consistent style of the rest of the file and name the
clock "omap_192m_alwon_fck" if the name of the struct clk is
omap_192m_alwon_ck.
> CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
> CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
> CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
> @@ -3390,6 +3438,8 @@ int __init omap2_clk_init(void)
> dpll4_m5_ck = dpll4_m5_ck_3630;
> dpll4_m6_ck = dpll4_m6_ck_3630;
> }
> + if (omap3_has_192mhz_clk())
> + omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
>
> clk_init(&omap2_clk_functions);
>
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index c81ec27..1bd52dc 100755
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -336,6 +336,8 @@
> #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
> #define OMAP3430_CLKSEL_L3_SHIFT 0
> #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
> +#define OMAP3630_CLKSEL_96M_SHIFT 12
> +#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
>
> /* CM_CLKSTCTRL_CORE */
> #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index a091b53..764334a 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -175,6 +175,8 @@ void __init omap3_check_features(void)
> OMAP3_CHECK_FEATURE(status, SGX);
> OMAP3_CHECK_FEATURE(status, NEON);
> OMAP3_CHECK_FEATURE(status, ISP);
> + if (cpu_is_omap3630())
> + omap3_features |= OMAP3_HAS_192MHZ_CLK;
>
> /*
> * TODO: Get additional info (where applicable)
> @@ -341,6 +343,7 @@ void __init omap3_cpuinfo(void)
> OMAP3_SHOW_FEATURE(sgx);
> OMAP3_SHOW_FEATURE(neon);
> OMAP3_SHOW_FEATURE(isp);
> + OMAP3_SHOW_FEATURE(192mhz_clk);
>
> printk(")\n");
> }
> diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
> index 9a028bd..6718e40 100644
> --- a/arch/arm/plat-omap/include/plat/cpu.h
> +++ b/arch/arm/plat-omap/include/plat/cpu.h
> @@ -500,6 +500,7 @@ extern u32 omap3_features;
> #define OMAP3_HAS_SGX BIT(2)
> #define OMAP3_HAS_NEON BIT(3)
> #define OMAP3_HAS_ISP BIT(4)
> +#define OMAP3_HAS_192MHZ_CLK BIT(5)
>
> #define OMAP3_HAS_FEATURE(feat,flag) \
> static inline unsigned int omap3_has_ ##feat(void) \
> @@ -512,5 +513,6 @@ OMAP3_HAS_FEATURE(sgx, SGX)
> OMAP3_HAS_FEATURE(iva, IVA)
> OMAP3_HAS_FEATURE(neon, NEON)
> OMAP3_HAS_FEATURE(isp, ISP)
> +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
>
> #endif
> --
> 1.5.6.3
>
> --
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- Paul
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