RE: [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support

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> From: Woodruff, Richard
> Sent: Tuesday, October 20, 2009 9:48 AM
> 
> 
> > From: Aguirre Rodriguez, Sergio Alberto
> > Sent: Tuesday, October 20, 2009 9:16 AM
> 
> > > + * lookup_dco_sddiv -j-type DPLL4 compensation variables
> >
> > Put a space before the j-type, and add better description.
> > Doesn't clarify what it really does IMHO:
> >
> > Something like:
> > "* lookup_dco_sddiv - Set j-type DPLL4 compensation variables"
> 
> For 45nm it was necessary to use a different DPLL IP for DPLL4 (dpllj).
> The other DPLLs are same which was used in 65nm (dpllm).  The register
> interface is slightly different.
> 
> Code could have said is type A or B, but simple choice was to follow
> internal name convention.
> 
Any comments on a neat handling of condition where clk->parent is NULL? A BUG_ON(!clk->parent) is good?

Regards,
Nishanth Menon
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