On 02/12/2024 16:45, Siddharth Vadapalli wrote: >>> the feature to be enabled/disabled via the ACSPCIE block are the same as >>> well i.e. "register layout can be inferred". The same goes for the >>> compatibles listed below in my previous reply i.e. they aren't bugs. >>> Same IP and integration across SoCs and hence reused in the sense of >>> Hardware and not Software. I hope this clarifies the rationale for the >>> "reuse". >> >> >> You mix re-use with fallback. These are almost never the same blocks, >> which you imply here. > > I know that the IP is the same, the bits are the same and those bits enable > the same functionality of the IP across the SoCs. If you still insist that > they are not same, I don't know what to say anymore. You can say what we have been saying on mailing lists all the time: hardware datasheets lie and sometimes you find one, tiny tiny difference. If you are uncertain, please consult your SoC maintainer on this matter. Best regards, Krzysztof
