From: Romain Naour <romain.naour@xxxxxxx> Unlike the SK-TDA4VM (k3-j721e-sk) board, there is no clock generator (CDCI6214RGET) on the BeagleBone AI-64 (k3-j721e-beagleboneai64) to provide PCIe refclk signal to PCIe Endponts. So the ACSPCIE module must provide refclk through PCIe_REFCLK pins. Use the new "ti,syscon-acspcie-proxy-ctrl" property to enable ACSPCIE module's PAD IO Buffers. Cc: Siddharth Vadapalli <s-vadapalli@xxxxxx> Signed-off-by: Romain Naour <romain.naour@xxxxxxx> --- With this patch, we can remove "HACK: Sierra: Drive clock out" patch applied on vendor kernel for BeagleBone AI-64: https://openbeagle.org/beagleboard/linux/-/commit/ad65d7ef675966cdbc5d75f2bd545fad1914ba9b v3: - update "acspcie0_proxy_ctrl" compatible to "ti,j721e-acspcie-proxy-ctrl" since this property is specific to j721e variant. v2: - use generic style comments - use "syscon" as generic node name for "acspcie0_proxy_ctrl" node - Keep the compatible "ti,j784s4-acspcie-proxy-ctrl" since the ACSPCIE buffer and its functionality is the same across all K3 SoCs. (Siddharth Vadapalli) "The compatible "ti,j784s4-acspcie-pcie-ctrl" should be reused for J721E and all other K3 SoCs. For example, see: https://lore.kernel.org/r/20240402105708.4114146-1-s-vadapalli@xxxxxx/ which introduced "ti,am62p-cpsw-mac-efuse" compatible. The same compatible is reused across all K3 SoCs: https://lore.kernel.org/r/20240628151518.40100-1-afd@xxxxxx/ " --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 5 +++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index fb899c99753e..741ad2ba6fdb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -859,6 +859,11 @@ &pcie1_rc { num-lanes = <2>; max-link-speed = <3>; reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; + /* + * There is no on-board or external reference clock generators, + * use refclk from the ACSPCIE module's PAD IO Buffers. + */ + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; }; &ufs_wrapper { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index af3d730154ac..32a232a90100 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy-ti.h> #include <dt-bindings/mux/mux.h> @@ -82,6 +83,11 @@ ehrpwm_tbclk: clock-controller@4140 { reg = <0x4140 0x18>; #clock-cells = <1>; }; + + acspcie0_proxy_ctrl: syscon@18090 { + compatible = "ti,j721e-acspcie-proxy-ctrl", "syscon"; + reg = <0x18090 0x4>; + }; }; main_ehrpwm0: pwm@3000000 { @@ -979,8 +985,8 @@ pcie1_rc: pcie@2910000 { max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; + clocks = <&k3_clks 240 1>, <&serdes1 CDNS_SIERRA_DERIVED_REFCLK>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; -- 2.45.0
