The DT node for the Dual-Cortex M3 IPU processor sub-system has
been added for OMAP4 SoCs. The L2RAM memory region information
has been added to the node through the 'reg' and 'reg-names'
properties. The node has the 'iommus', 'clocks', 'resets',
'mboxes' and 'firmware' properties also added, and is disabled
for now. It should be enabled as per the individual product
configuration in the corresponding board dts files.
Signed-off-by: Suman Anna <s-anna@xxxxxx>
---
arch/arm/boot/dts/omap4.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 8f6b38bb5753..4928951ad9db 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -284,6 +284,18 @@ dsp: dsp {
status = "disabled";
};
+ ipu: ipu@55020000 {
+ compatible = "ti,omap4-ipu";
+ reg = <0x55020000 0x10000>;
+ reg-names = "l2ram";
+ iommus = <&mmu_ipu>;
+ resets = <&prm_core 0>, <&prm_core 1>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ firmware-name = "omap4-ipu-fw.xem3";
+ mboxes = <&mailbox &mbox_ipu>;
+ status = "disabled";
+ };
+
aes1_target: target-module@4b501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b501080 0x4>,
--
2.26.0
