* Lokesh Vutla <lokeshvutla@xxxxxx> [200310 07:06]: > Hi Tony, > > [...snip...] > > >>>> > >>>> + /* > >>>> + * Disable auto reload so that the current cycle gets completed and > >>>> + * then the counter stops. > >>>> + */ > >>>> mutex_lock(&omap->mutex); > >>>> - omap->pdata->stop(omap->dm_timer); > >>>> + omap->pdata->set_pwm(omap->dm_timer, > >>>> + pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED, > >>>> + true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE, > >>>> + false); > >>>> + > >>>> mutex_unlock(&omap->mutex); > >>>> } > >>> > >>> I'm seeing an issue with this patch where after use something is > >>> left on and power consumption stays higher by about 30 mW after > >>> use. > >> > >> Interesting...What is the PWM period and duty cycle in the test case? > >> Can you dump the following registers before and after disabling: > >> - TLDR > >> - TMAR > >> - TCLR > > > > Here's the state dumped before and after in omap_dm_timer_set_pwm(): > > > > omap_timer 4803e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00000040 > > omap_timer 4803e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001842 > > omap_timer 4013e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00000040 > > omap_timer 4013e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001842 > > omap_timer 4013e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00001843 > > omap_timer 4013e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001841 > > omap_timer 4803e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00001843 > > omap_timer 4803e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001841 > > > > Looking at the registers: > period = 327 *(1000/clk_freq in MHz) ns > duty_cycle = perioid. > > I did simulate this behavior on BeagleBoneBlack on timer7. PWM is going down > after disabling. > > > So looks like the start bit is still enabled after use? > > Right, that is expected. The start bit gets disabled automatically once the pwm > period completes. This is because auto reload bit is off. That's the main idea > of this patch so that PWM period is completed after disabling, else PWM is > stopped abruptly. OK > Not sure why it is not happening in your case. If you think it is not needed, I > can drop this patch and add a limitation saying that PWM gets disabled > immediately without completing the current cycle. Could it be that we now have the cpu_pm notifier restore something invalid after exiting idle that restarts the counter? Regards, Tony
