* Lokesh Vutla <lokeshvutla@xxxxxx> [200309 04:53]:
> Hi Tony,
>
> On 06/03/20 11:44 PM, Tony Lindgren wrote:
> > * Lokesh Vutla <lokeshvutla@xxxxxx> [200228 09:58]:
> >> pwm_omap_dmtimer_disable() calls .stop callback which abruptly stops the
> >> timer counter. This doesn't complete the current pwm cycle and
> >> immediately disables the pwm. Instead disable the auto reload
> >> functionality which allows to complete the current pwm cycle and then
> >> disables the timer.
> >>
> >> Signed-off-by: Lokesh Vutla <lokeshvutla@xxxxxx>
> >> ---
> >> drivers/pwm/pwm-omap-dmtimer.c | 10 +++++++++-
> >> 1 file changed, 9 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c
> >> index bc338619232d..89b3c25d02b8 100644
> >> --- a/drivers/pwm/pwm-omap-dmtimer.c
> >> +++ b/drivers/pwm/pwm-omap-dmtimer.c
> >> @@ -93,8 +93,16 @@ static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
> >> {
> >> struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
> >>
> >> + /*
> >> + * Disable auto reload so that the current cycle gets completed and
> >> + * then the counter stops.
> >> + */
> >> mutex_lock(&omap->mutex);
> >> - omap->pdata->stop(omap->dm_timer);
> >> + omap->pdata->set_pwm(omap->dm_timer,
> >> + pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
> >> + true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
> >> + false);
> >> +
> >> mutex_unlock(&omap->mutex);
> >> }
> >
> > I'm seeing an issue with this patch where after use something is
> > left on and power consumption stays higher by about 30 mW after
> > use.
>
> Interesting...What is the PWM period and duty cycle in the test case?
> Can you dump the following registers before and after disabling:
> - TLDR
> - TMAR
> - TCLR
Here's the state dumped before and after in omap_dm_timer_set_pwm():
omap_timer 4803e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00000040
omap_timer 4803e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001842
omap_timer 4013e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00000040
omap_timer 4013e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001842
omap_timer 4013e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00001843
omap_timer 4013e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001841
omap_timer 4803e000.timer: XXX set_pwm before: tldr: fffffeb8 tmar: fffffffe tclr: 00001843
omap_timer 4803e000.timer: XXX set_pwm after: tldr: fffffeb8 tmar: fffffffe tclr: 00001841
So looks like the start bit is still enabled after use?
I think the duty cycle depends on the strength set for rumble-test.c.
> > I can reproduce this easily on droid4 with Sebastian's rumble-test
> > app[0]. After use, I sometimes also hear the vibrator keep chirping
> > quietly, so there seems to be some pwm still happening after disable :)
>
> hmm..The line clearly goes down on the scope after the current pwm duty cycle is
> done and never comes back.
OK
Regards,
Tony
