On 12/10/2019 8:38 PM, Jean Pihet wrote: > Vignesh, > > On Tue, Dec 10, 2019 at 2:17 PM Vignesh Raghavendra <vigneshr@xxxxxx> wrote: [...] >> Ah, sorry, there is no CS toggle, so this case will work. Although its >> less efficient as you could have set WLEN to 32 and read entire >> QSPI_SPI_DATA_REG in one transaction. >> >> But this patch definitely changes the behvior when t->rx_nbits = 4 and >> t->bits_per_word = 32. Previous code did: >> >> *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); >> >> This patch does: >> >> + rx = readl(qspi->base + QSPI_SPI_DATA_REG); >> [...] >> + case SPI_NBITS_QUAD: >> + if (count >= 1) >> + *rxbuf++ = rx >> 24; >> + if (count >= 2) >> + *rxbuf++ = rx >> 16; >> + if (count >= 3) >> + *rxbuf++ = rx >> 8; >> + if (count >= 4) >> + *rxbuf++ = rx; >> >> >> So there is change in the endianess... > Oh! The cases where bits_per_word is different than 8 definitely needs > more thinking. I have tested the patches > with SPI flash only. How to test it with 32 bits per word? > My suggestion would be to restrict optimizations to just address SPI Flash usecase, i.e t->bits_per_word == 8. And not touch any other word sizes. See qspi_write_msg() on how this can be done for Single bit mode, same can be extended for other modes. Regards Vignesh
