The QSPI IP is clocked by two clocks:
- CORE_CLKOUTM4 / 2 (L3) as interface clock,
- PER_CLKOUTM2 / 4 (L4) as functional clock, which is PER_CLKOUTM2
divided by 4, so at 192Mhz / 4 = 48MHz.
Fix the use of the correct fclk by the driver and fix the frequency
value so that the divider is correctly programmed to generate the
desired frequency of QSPI_CLK.
---
drivers/spi/spi-ti-qspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3cb65371ae3b..4680dad38ab2 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -79,7 +79,7 @@ struct ti_qspi {
#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
-#define QSPI_FCLK 192000000
+#define QSPI_FCLK 48000000
/* Clock Control */
#define QSPI_CLK_EN (1 << 31)
@@ -748,7 +748,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
}
}
- qspi->fclk = devm_clk_get(&pdev->dev, "fck");
+ qspi->fclk = devm_clk_get(&pdev->dev, "dpll_per_m2_div4_ck");
if (IS_ERR(qspi->fclk)) {
ret = PTR_ERR(qspi->fclk);
dev_err(&pdev->dev, "could not get clk: %d\n", ret);
--
2.23.0
