* Grygorii Strashko <grygorii.strashko@xxxxxx> [191118 21:09]: > > > On 18/11/2019 16:50, Tony Lindgren wrote: > > * Grygorii Strashko <grygorii.strashko@xxxxxx> [191118 12:20]: > > > The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0) > > > is specified incorrectly, which is caused incorrect MDIO bus clock > > > configuration MDCLK. The correct CPSW MDIO functional clock is > > > gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it. > > > > OK. Is this dra7 only, or are the other mdio clocks changed in commit > > 1faa415c9c6e wrong too? > > only DRA7. OK thanks for confirming that. Tony
