* Grygorii Strashko <grygorii.strashko@xxxxxx> [191113 10:02]:
>
>
> On 11/11/2019 19:12, Tony Lindgren wrote:
> > * Grygorii Strashko <grygorii.strashko@xxxxxx> [191109 14:21]:
> > > The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
> > > of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
> > > Hence, fix it.
> > >
> > > Fixes: commit dffa9051d546 ('clk: ti: dra7: add new clkctrl data')
> > > Signed-off-by: Grygorii Strashko <grygorii.strashko@xxxxxx>
> >
> > Hmm is there a mux for the source though?
>
> Not sure what do you mean here :(
>
> fck clock for CPSW and MDIO is "gmac_main_clk" which is 125MHz and
> that what need to be passed to drivers and enabled through the clock tree.
> The TI specific PM is handled by gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0
> which required sysc programming and child modules dosn't need to even know that.
OK
> So, this patch is simply correct clock tree for dra7:
> dpll_gmac_ck -> .... -> gmac_main_clk -> gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0
So I guess there's no mux clock for DRA7_GMAC_GMAC_CLKCTRL 0.
What I meant is maybe check also that no top level mux is needed
similar to what we have for these configured with assigned-clocks:
$ git grep -C3 assigned-clock arch/arm/boot/dts/dra7*
> Seems MDIO dt also need to be fixed to use:
> gmac_main_clk as "fck". I'll try and send patch.
OK
> By the way, the patch follows am3/am4 (am4_cpsw_125mhz_clkctrl_regs,
> am3_cpsw_125mhz_clkctrl_regs)
OK
Tony
