* Grygorii Strashko <grygorii.strashko@xxxxxx> [191109 14:21]:
> The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
> of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
> Hence, fix it.
>
> Fixes: commit dffa9051d546 ('clk: ti: dra7: add new clkctrl data')
> Signed-off-by: Grygorii Strashko <grygorii.strashko@xxxxxx>
Hmm is there a mux for the source though?
In that case using assigned-clocks and assigned-clock-parents in
addition to a related clk-7xx.c fix would be needed.
Regards,
Tony
> ---
> drivers/clk/ti/clk-7xx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
> index 9dd6185a4b4e..66e4b2b9ec60 100644
> --- a/drivers/clk/ti/clk-7xx.c
> +++ b/drivers/clk/ti/clk-7xx.c
> @@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
> };
>
> static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
> - { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
> + { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
> { 0 },
> };
>
> --
> 2.17.1
>
