On Tuesday 10 September 2019 11:21:34 Adam Ford wrote: > According to a note in omap_hwmod_3xxx_data.c, > > /* > * Apparently the SHA/MD5 and AES accelerator IP blocks are > * only present on some AM35xx chips, and no one knows which > * ones. See > * http://www.spinics.net/lists/arm-kernel/msg215466.html So > * if you need these IP blocks on an AM35xx, try uncommenting > * the following lines. > */ > > I decided to uncomment the hwmod entries, and I got the following: > > [ 0.263222] omap_hwmod: sham: _wait_target_ready failed: -16 > [ 0.263248] omap_hwmod: sham: cannot be enabled for reset (3) > [ 0.265837] omap_hwmod: aes: _wait_target_ready failed: -16 > [ 0.265851] omap_hwmod: aes: cannot be enabled for reset (3) > [ 6.208866] omap_hwmod: sham: _wait_target_ready failed: -16 > [ 6.287732] omap_hwmod: aes: _wait_target_ready failed: -16 Hi! Same errors I got in qemu-n900, but not on real N900. So I guess those errors means that IP blocks are not present. > Based on this, I wonder if the sham and aes modules are not present. > If this is the case, it might explain why I cannot use the rng either. Probably this is the reason, you do not have crypto/rng HW engine. -- Pali Rohár pali.rohar@xxxxxxxxx
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