GPIO3/4 and MCSPI2/3/4 are now present. Lightly tested on am3874
platform.
Signed-off-by: Graeme Smecher <gsmecher@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/dm814x.dtsi | 64 ++++++++++-
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 117 +++++++++++++++++++++
2 files changed, 180 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 601c57afd4fe..f044abd64b7e 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -222,6 +222,30 @@
#interrupt-cells = <2>;
};
+ gpio3: gpio@1ac000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio3";
+ ti,gpio-always-on;
+ reg = <0x1ac000 0x2000>;
+ interrupts = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@1ae000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio4";
+ ti,gpio-always-on;
+ reg = <0x1ae000 0x2000>;
+ interrupts = <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
i2c2: i2c@2a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
@@ -240,10 +264,48 @@
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
dmas = <&edma 16 0 &edma 17 0
- &edma 18 0 &edma 19 0>;
+ &edma 18 0 &edma 19 0
+ &edma 20 0 &edma 21 0
+ &edma 22 0 &edma 23 0>;
+
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+
+ mcspi2: spi@1a0000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x1a0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <125>;
+ ti,spi-num-cs = <4>;
+ ti,hwmods = "mcspi2";
+ dmas = <&edma 42 0 &edma 43 0
+ &edma 44 0 &edma 45 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
+ /* Board must configure dmas with edma_xbar for EDMA */
+ mcspi3: spi@1a2000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x1a2000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <126>;
+ ti,spi-num-cs = <4>;
+ ti,hwmods = "mcspi3";
+ };
+
+ mcspi4: spi@1a4000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x1a4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <127>;
+ ti,spi-num-cs = <4>;
+ ti,hwmods = "mcspi4";
+ };
+
timer1: timer@2e000 {
compatible = "ti,dm814-timer";
reg = <0x2e000 0x2000>;
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 1ca8710ff29e..debcd88ab971 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -539,6 +539,58 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
.user = OCP_USER_MPU,
};
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "sysclk18_ck" },
+};
+
+static struct omap_hwmod dm81xx_gpio3_hwmod = {
+ .name = "gpio3",
+ .clkdm_name = "alwon_l3s_clkdm",
+ .class = &dm81xx_gpio_hwmod_class,
+ .main_clk = "sysclk6_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
+ .master = &dm81xx_l4_ls_hwmod,
+ .slave = &dm81xx_gpio3_hwmod,
+ .clk = "sysclk6_ck",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "sysclk18_ck" },
+};
+
+static struct omap_hwmod dm81xx_gpio4_hwmod = {
+ .name = "gpio4",
+ .clkdm_name = "alwon_l3s_clkdm",
+ .class = &dm81xx_gpio_hwmod_class,
+ .main_clk = "sysclk6_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
+ .master = &dm81xx_l4_ls_hwmod,
+ .slave = &dm81xx_gpio4_hwmod,
+ .clk = "sysclk6_ck",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
@@ -1133,6 +1185,45 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = {
.class = &dm816x_mcspi_class,
};
+static struct omap_hwmod dm81xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .clkdm_name = "alwon_l3s_clkdm",
+ .main_clk = "sysclk10_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .class = &dm816x_mcspi_class,
+};
+
+static struct omap_hwmod dm81xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .clkdm_name = "alwon_l3s_clkdm",
+ .main_clk = "sysclk10_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .class = &dm816x_mcspi_class,
+};
+
+static struct omap_hwmod dm81xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .clkdm_name = "alwon_l3s_clkdm",
+ .main_clk = "sysclk10_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .class = &dm816x_mcspi_class,
+};
+
static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_mcspi1_hwmod,
@@ -1140,6 +1231,27 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
.user = OCP_USER_MPU,
};
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
+ .master = &dm81xx_l4_ls_hwmod,
+ .slave = &dm81xx_mcspi2_hwmod,
+ .clk = "sysclk6_ck",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
+ .master = &dm81xx_l4_ls_hwmod,
+ .slave = &dm81xx_mcspi3_hwmod,
+ .clk = "sysclk6_ck",
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
+ .master = &dm81xx_l4_ls_hwmod,
+ .slave = &dm81xx_mcspi4_hwmod,
+ .clk = "sysclk6_ck",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
@@ -1378,8 +1490,13 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__i2c2,
&dm81xx_l4_ls__gpio1,
&dm81xx_l4_ls__gpio2,
+ &dm81xx_l4_ls__gpio3,
+ &dm81xx_l4_ls__gpio4,
&dm81xx_l4_ls__elm,
&dm81xx_l4_ls__mcspi1,
+ &dm81xx_l4_ls__mcspi2,
+ &dm81xx_l4_ls__mcspi3,
+ &dm81xx_l4_ls__mcspi4,
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
&ti81xx_l4_ls__rtc,
--
2.19.2
