> > Could you try this patch with your TS GPIO configured as > level-triggered? > > Kevin > I tried the below patch, it can solve the issue also. > commit f8eb69a2edd684c9e0b72bc3c84c6af9718bd4a4 > Author: Kevin Hilman <khilman@xxxxxxxxxxxxxxxxxxx> > Date: Thu Jun 4 15:57:10 2009 -0700 > > OMAP: GPIO: clear/restore level/edge detect settings on > mask/unmask > > <needs detailed description> > > Signed-off-by: Kevin Hilman <khilman@xxxxxxxxxxxxxxxxxxxxxx> > > diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c > index 3b2054b..83ac494 100644 > --- a/arch/arm/plat-omap/gpio.c > +++ b/arch/arm/plat-omap/gpio.c > @@ -1135,6 +1135,7 @@ static void gpio_mask_irq(unsigned int irq) > struct gpio_bank *bank = get_irq_chip_data(irq); > > _set_gpio_irqenable(bank, gpio, 0); > + _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); > } > > static void gpio_unmask_irq(unsigned int irq) > @@ -1142,6 +1143,11 @@ static void gpio_unmask_irq(unsigned int irq) > unsigned int gpio = irq - IH_GPIO_BASE; > struct gpio_bank *bank = get_irq_chip_data(irq); > unsigned int irq_mask = 1 << get_gpio_index(gpio); > + struct irq_desc *desc = irq_to_desc(irq); > + u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; > + > + if (trigger) > + _set_gpio_triggering(bank, > get_gpio_index(gpio), trigger); > > /* For level-triggered GPIOs, the clearing must be done after > * the HW source is cleared, thus after the handler has run */ > -- > To unsubscribe from this list: send the line "unsubscribe > linux-omap" in > the body of a message to majordomo@xxxxxxxxxxxxxxx > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
