* Andreas Kemnade <andreas@xxxxxxxxxxxx> [180907 16:52]:
> sdio irq + wakeirq via remapped dat1 as gpio + 4 bit -(=reverted)
> generic_wakeirq_patch = does not work
And here's where I suspect that in deeper SoC idle states
with floating lines confuse the SDIO card :)
Maybe try adding pinctrl "idle" state that puts the rest
of the SDIO pins to safe mode (7) and see if that helps?
The omap_hsmmc.c driver should already support that.
> > I fairly regularly test the mainline kernel with omap3
> > hitting off mode during idle with wlan connected and
> > things are working for me with no issues and the device
> > wakes to a ping over wlan just fine.
>
> What sdio device are you testing 1bit or 4bit? with or without
> level shifter in between?
I've tested with mwifiex_sdio and wlcore. For testing
wlcore on omap3-evm, the following pending patch is still
needed though to keep the SoC off mode glitch from powering
down wlcore.
> At least I now have a working not-so-clean solution, so I have a base to
> experiment and analyze to get a better solution.
But.. I suspect it just works now as it somehow blocks
SoC deeper idle states though :)
> (*) here probably comes into account that the wlan chip is powered of
> and as a side effect dat1 gets low (through a level shifter).
> As the generic wakeup irq is not turned off (contrary to the older
> solution) when sdio irq is disabled, it will always runtime resume
> quickly.
I guess it's possible that you now have the SoC entering
off mode during idle and have a glitch on the power
GPIO as omap3-evm has.
Regards,
Tony
8< ----------------------------
--- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
@@ -133,7 +133,7 @@
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */
+ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */
OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
>;
};
--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -122,6 +122,7 @@
};
&mmc2 {
+ interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
vmmc-supply = <&wl12xx_vmmc>;
non-removable;
bus-width = <4>;
@@ -132,8 +133,10 @@
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
- interrupt-parent = <&gpio5>;
- interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */
+ /* gpio_149 with uart1_rts pad as wakeirq */
+ interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>,
+ <&omap3_pmx_core 0x14e>;
+ interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>;
};
};
--- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
@@ -86,6 +86,10 @@
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
>;
};
