Hi Ralf,
Thanks for the patch. I have been unable to reproduce an MMU fault in
order to verify the fix, but I have confirmed that the cache flushes are
indeed done on the right memory locations with this patch.
On 08/01/2018 09:50 AM, Ralf Goebel wrote:
> The base address used for DMA operations did incorrectly include
> the offset for the table entry. The entry offset was then added
> again which lead to incorrect behavior.
>
> The calculation of the base address is changed to point to the
> beginning of the table.
Can you please revise the patch header and description to reflect "L2"
table entry. L1 entries are flushed properly, so were working just fine
even before.
Also, please add the Fixes tag and Cc the iommu list while reposting.
Fixes: bfee0cf0ee1d ("iommu/omap: Use DMA-API for performing cache flushes")
With those,
Acked-by: Suman Anna <s-anna@xxxxxx>
Joerg,
It is probably too late for v4.18 at this point, can you queue the
reposted patch for v4.19 and we can have the fix come through stable for
4.18 and earlier kernels.
regards
Suman
>
> Signed-off-by: Ralf Goebel <ralf.goebel@xxxxxxxxxxxxxxxxxxxxxx>
> ---
> drivers/iommu/omap-iommu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
> index af4a8e7fcd27..3b05117118c3 100644
> --- a/drivers/iommu/omap-iommu.c
> +++ b/drivers/iommu/omap-iommu.c
> @@ -550,7 +550,7 @@ static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd,
>
> pte_ready:
> iopte = iopte_offset(iopgd, da);
> - *pt_dma = virt_to_phys(iopte);
> + *pt_dma = iopgd_page_paddr(iopgd);
> dev_vdbg(obj->dev,
> "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
> __func__, da, iopgd, *iopgd, iopte, *iopte);
> @@ -738,7 +738,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
> }
> bytes *= nent;
> memset(iopte, 0, nent * sizeof(*iopte));
> - pt_dma = virt_to_phys(iopte);
> + pt_dma = iopgd_page_paddr(iopgd);
> flush_iopte_range(obj->dev, pt_dma, pt_offset, nent);
>
> /*
>
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