Hi,
I think the offsets used for flushing the page table entries in
iopte_alloc_page(), iopte_alloc_large() and iopgtable_clear_entry_core() are
incorrect. The offsets are already included in pt_dma and therefore they
should be zero.
The problem occurred while adding support for System MMU2 (PCIe) on a
AM5728.
An exception occurs during a memory write from a device into memory:
[ 63.607203] WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147
l3_interrupt_handler+0x25c/0x36c
[ 63.616373] 44000000.ocp:L3 Custom Error: MASTER PCIE1 TARGET MMU2
(Idle): Data Access in User mode during Functional access
[ 63.627633] Modules linked in: agexpcidrv(O)
[ 63.631934] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G O
4.9.59-rt23-visioncam-xm+ #38
[ 63.640839] Hardware name: Generic DRA74X (Flattened Device Tree)
[ 63.646953] Backtrace:
...
[ 63.916445] iommu_report_fault(): status = 0x00000002
[ 63.916456] omap-iommu 4881e000.mmu: 4881e000.mmu: errs:0x00000002
da:0x80002f80 pgd:0xeeba6000 *pgd:0xad989c01 pte:0xed989c08 *pte:0xb73d7002
According to TI documentation, this error (status = 0x00000002) is caused by
an invalid descriptor in the translation tables (TRANSLATIONFAULT).
The following change in the functions mentioned above fixed the problem:
flush_iopte_range(obj->dev, pt_dma, 0/*offset*/, ...);
Can someone verify this?
Thanks,
Ralf
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